This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Reliable Butterfly Distributed-Memory Multiprocessors
September 1994 (vol. 43 no. 9)
pp. 1004-1013

Since the butterfly network possesses various attractive topological properties and its constituent node has a fixed degree, independent of the system size, interconnecting processors in accordance with the butterfly topology to construct a distributed-memory multiprocessor is advantageous, especially for a large sized system. Every butterfly node in a multiprocessor so constructed is a processor, not simply a switch. In this paper, we examine a reliable butterfly-based multiprocessor that preserves its full rigid butterfly configuration even in the presence of faults. The proposed butterfly parallel system can tolerate any single and many multiple node/link failures, giving rise to significantly improved reliability. Reconfiguration in response to an operational fault in our design is easy and may be performed in a distributed manner. A system after reconfiguration is ensured to provide the same high performance. Reliability results show that our design compares favorably with an earlier design. An extension to this reliable design is also addressed.

[1] R. R. Koch, "Increasing the size of a network by a constant factor can increase performance by more than a constant factor," inProc. 29th Annu. Symp. Foundations Comput. Sci., IEEE, Oct. 1988, pp. 221-230.
[2] E. Upfal, "AnO(logN) deterministic packet routing scheme," inProc. 21st Annu. ACM Symp. Theory Comput., May 1989, pp. 241-250.
[3] T. Leighton and B. Maggs, "Expanders might be practical: Fast algorithms for routing around faults on multibutterflies," inProc. 30th Annu. IEEE Symp. Foundations Comput. Sci., 1989, pp. 384-389.
[4] C.-L. Wu and T.-Y. Feng, "On a class of multistage interconnection networks,"IEEE Trans. Comput., vol. C-29, pp. 694-702, Aug. 1980.
[5] L. M. Napolitano, Jr., "The design of a high performance packet-switched network storage system,"J. Parallel and Distrib. Comput., vol. 10, pp. 103-114, Oct. 1990.
[6] B. Grey, A. Avizienis, and D. Rennels, "A fault-tolerant architecture for network storage systems," inProc. 14th Int. Symp. Fault-Tolerant Computing, June 1984, pp. 232-239.
[7] V. Balasubramanian and P. Banerjee, "A fault-tolerant massively parallel processing architecture,"J. Parallel Distributed Computing, vol. 4, pp. 363-383, 1987.
[8] M. Blatt, "Effects of switch failure on soft-configurable WSI yield," inProc. 1990 Int. Conf. Wafer Scale Integration, Jan. 1990, pp. 152-159.
[9] I. Koren and M. A. Breuer, "On area and yield considerations for fault-tolerant VLSI processor arrays,"IEEE Trans. Comput., vol. C-33, pp. 21-27, Jan. 1984.
[10] G. B. Adams, III and H. J. Siegel, "The extra stage cube: A fault-tolerant interconnection network for supersystems,"IEEE Trans. Comput., vol. C-31, pp. 443-454, May 1982.
[11] S.-Y. Kuo and W.K. Fuchs, "Reconfigurable cube-connected cycles architectures,"J. Parallel Distributed Comput., vol. 9, pp. 1-10, May 1990.
[12] M. C. Howells and V. K. Agarwal, "A reconfiguration scheme for yield enhancement of large area binary tree architectures,"IEEE Trans. Comput., vol. 37, pp. 463-468, Apr. 1988.

Index Terms:
network topology; fault tolerant computing; reliability; distributed memory systems; reconfigurable architectures; parallel architectures; multiprocessor interconnection networks; distributed-memory multiprocessors; reliability; butterfly network; topological properties; processor interconnection; operational faults; parallel system; node failures; link failures; reconfiguration; performance; design.
Citation:
Nian-Feng Tzeng, "Reliable Butterfly Distributed-Memory Multiprocessors," IEEE Transactions on Computers, vol. 43, no. 9, pp. 1004-1013, Sept. 1994, doi:10.1109/12.312111
Usage of this product signifies your acceptance of the Terms of Use.