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Hardware Designs for Exactly Rounded Elementary Functions
August 1994 (vol. 43 no. 8)
pp. 964-973

This paper presents hardware designs that produce exactly rounded results for the functions of reciprocal, square-root, 2/sup x/, and log/sub 2/(x). These designs use polynomial approximation in which the terms in the approximation are generated in parallel, and then summed by using a multi-operand adder. To reduce the number of terms in the approximation, the input interval is partitioned into subintervals of equal size, and different coefficients are used for each subinterval. The coefficients used in the approximation are initially determined based on the Chebyshev series approximation. They are then adjusted to obtain exactly rounded results for all inputs. Hardware designs are presented, and delay and area comparisons are made based on the degree of the approximating polynomial and the accuracy of the final result. For single-precision floating point numbers, a design that produces exactly rounded results for all four functions has an estimated delay of 80 ns and a total chip area of 98 mm/sup 2/ in a 1.0-micron CMOS technology. Allowing the results to have a maximum error of one unit in the last place reduces the computational delay by 5% to 30% and the area requirements by 33% to 77%.

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Index Terms:
CMOS integrated circuits; digital arithmetic; Chebyshev approximation; approximation theory; polynomials; summing circuits; multiplying circuits; hardware designs; exactly rounded elementary functions; reciprocal; square-root; polynomial approximation; multi-operand adder; Chebyshev series approximation; single-precision floating point numbers; chip area; 1.0-micron CMOS technology; computational delay; computer arithmetic; exact rounding; parallel multiplier; argument reduction; special-purpose hardware; 1 micron.
Citation:
M.J. Schulte, E.E. Swartzlander, Jr., "Hardware Designs for Exactly Rounded Elementary Functions," IEEE Transactions on Computers, vol. 43, no. 8, pp. 964-973, Aug. 1994, doi:10.1109/12.295858
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