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A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms
August 1994 (vol. 43 no. 8)
pp. 892-898

A very simple multiplier cell is developed for use in a linear, purely systolic array forming a digit-serial multiplier for unsigned or 2'complement operands. Each cell produces two digit-product terms and accumulates these into a previous sum of the same weight, developing the product least significant digit first. Grouping two terms per cell, the ratio of active elements to latches is low, and only upper bound [n]/2 cells are needed for a full n by n multiply. A module-multiplier is then developed by incorporating a Montgomery type of module-reduction. Two such multipliers interconnect to form a purely systolic module exponentiator, capable of performing RSA encryption at very high clock frequencies, but with a low gate count and small area. It is also shown how the multiplier, with some simple back-end connections, can compute modular inverses and perform modular division for a power of two as modulus.

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Index Terms:
cryptography; digital arithmetic; multiplying circuits; systolic arrays; logic design; systolic linear-array multiplier; right-shift algorithms; multiplier cell; systolic array; digit-serial multiplier; digit-product terms; least significant digit first; active elements; latches; module-multiplier; Montgomery module-reduction; RSA encryption; modular inverses; modular division; Hensel codes.
P. Kornerup, "A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms," IEEE Transactions on Computers, vol. 43, no. 8, pp. 892-898, Aug. 1994, doi:10.1109/12.295851
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