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Addendum to "Hierarchical Scalable Photonic Architectures for High-Performance Processor Interconnection"
July 1994 (vol. 43 no. 7)
pp. 864

The above paper by L. Bhuyan and D.P. Agrawal (1984) described a hierarchical, all-optical wavelength division multiplexed (WDM) network that is being built to support the communication requirements of a large distributed shared memory system. Dynamically adaptable bandwidth allocation is supported, both within and between levels of the hierarchy, and is highly scalable through wavelength re-use at each hierarchical level. The mixed radix scheme introduced was used for processor numbering, but was not specified. The system was described in term of a time multiplexed access protocol, generalized to the multichannel WDM environment, which has static slot assignment that provides excellent throughput but long latencies due to cycle synchronization. The actual system implementation will use a hybrid WDMA strategy, which is collisionless, provides low latency support, dynamic bandwidth allocation within a hierarchical level, and a fast reliable broadcast.

[1] L. Bhuyan and D. P. Agrawal, "Generalized hypercube and hyperbus structures for a computer network,"IEEE Trans. Comput., vol. C-33, pp. 323-333, Apr. 1984.
[2] P. Dowd and K. M. Sivalingam, "A multi-level WDM access protocol for an optically inter- connected parallel computer," inProc. IEEE INFOCOM'94, Toronto, ON, Canada, June 1994.
[3] R. Minnich, "An CC-24 low latency network interface," Tech. Rep. SRC-93-111, Supercomputing Res. Center, Bowie, MD, Dec. 1993.

Index Terms:
hypercube networks; optical information processing; wavelength division multiplexing; hierarchical scalable photonic architectures; high-performance processor interconnection; all-optical wavelength division multiplexed network; distributed shared memory system; bandwidth allocation; processor numbering; time multiplexed access protocol; static slot assignment; cycle synchronization.
Citation:
P.W. Dowd, K.K. Bogineni, K.A. Aly, J.A. Perreault, "Addendum to "Hierarchical Scalable Photonic Architectures for High-Performance Processor Interconnection"," IEEE Transactions on Computers, vol. 43, no. 7, pp. 864, July 1994, doi:10.1109/12.293268
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