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Issue No.07 - July (1994 vol.43)
pp: 841-848
ABSTRACT
<p>This paper discusses the design of two reconfiguration strategies for distributed memory multicomputer architectures under failures. The specific architectures to which we apply the techniques are hypercubes and meshes. The first scheme uses spare processors attached to certain processors in the hypercube or mash using a novel embedding technique. The second approach places spare processors along specific links in the hypercube or mesh. Both schemes involve the mapping of logical links of a virtual machine onto a set of physical links in the final reconfigured machine and hence suffer some performance degradation. We characterize the performance degradation through trace-driven simulation of real applications running on the faulty and reconfigured system. We find that the schemes have high reliability, suffer little degradation in performance, and are very low in cost.</p>
INDEX TERMS
hypercube networks; reconfigurable architectures; discrete event simulation; performance evaluation; distributed memory systems; hardware strategies; reconfiguring hypercubes; reconfiguring meshes; distributed memory multicomputer architectures; embedding technique; logical links mapping; virtual machine; performance degradation; trace-driven simulation.
CITATION
P. Banerjee, M. Peercy, "Design and Evaluation of Hardware Strategies for Reconfiguring Hypercubes and Meshes Under Faults", IEEE Transactions on Computers, vol.43, no. 7, pp. 841-848, July 1994, doi:10.1109/12.293264
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