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Bit-Level Systolic Array for Fast Exponentiation in GF(2/sup m/)
July 1994 (vol. 43 no. 7)
pp. 838-841

This paper presents a new parallel-in-parallel-out bit-level systolic array with unidirectional data flow for computing exponentiation in GF(2/sup m/). The array is highly regular, modular, and thus well suited to very-large-scale-integration implementation. In addition, it can provide the maximum throughput in the sense of producing new results at a rate of one per clock cycle. As compared with a previously known systolic GF(2/sup m/) exponentiator with the same throughput performance, the proposed system requires much less chip area, has small latency, and is easier to incorporate fault-tolerant design.

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Index Terms:
VLSI; systolic arrays; fault tolerant computing; bit-level systolic array; fast exponentiation; unidirectional data flow; very-large-scale-integration implementation; small latency; fault-tolerant design.
Chin-Liang Wang, "Bit-Level Systolic Array for Fast Exponentiation in GF(2/sup m/)," IEEE Transactions on Computers, vol. 43, no. 7, pp. 838-841, July 1994, doi:10.1109/12.293263
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