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Performance Analysis of Multilevel Bus Networks for Hierarchical Multiprocessors
July 1994 (vol. 43 no. 7)
pp. 789-805

A multiple bus system provides more bandwidth and a high degree of fault tolerance than a single bus system. But such a system becomes very expensive for a large number of processors and memory modules, due to the requirement of too many connections (switches). Lang (1983) proposed a different bus-based system, known as the partial multiple bus system, which requires a lower number of connections than a multiple bus system, but with a slight degradation in system performance. This paper presents a new type of bus-based system, called the multilevel bus system. Such a bus architecture can be used to design hierarchical multiprocessors. This bus-based system requires significantly less connections than multiple and partial multiple bus systems. This system is very cost-effective, as compared to multiple and partial multiple bus systems, when there exists some locality in the computations. Analytical and simulation models have been developed to determine the performance of both synchronous and asynchronous multilevel bus systems. The results obtained from the analysis show that a multilevel bus system performs fairly close to other bus-based systems for the hierarchical reference (HR) model. In the HR model, a processor accesses its nearest memory modules more frequently than other memory modules.

[1] T. Lang, M. Valero, and M. A. Fiol, "Reduction of connections for multibus' organization,"IEEE Trans. Comput., vol. C-32, no. 8, pp. 707-716, Aug. 1983.
[2] T. Lang, M. Valero, and I. Alegre, "Bandwidth of crossbar and multiple-bus connections for multiprocessors,"IEEE Trans. Comput., vol. C-31, no. 12, pp. 1227-1234, Dec. 1982.
[3] C.R. Das and L.N. Bhuyan, "Bandwidth Availability of Multiple-bus Multiprocessors,"IEEE Trans. Computers, Vol C-34, Oct. 1985, pp. 918-926.
[4] L. N. Bhuyan, "A combinatorial analysis of multibus multiprocessors," inProc. 1984 Int. Conf. Parallel Processing, 1984, pp. 225-227.
[5] T.N. Mudgeet al., "Analysis of multiple bus interconnection networks," inProc. 1984 Int. Conf. Parallel Processing, Aug. 21-24, 1984, pp. 228-232.
[6] W.-T. Chen and J.-P. Sheu, "Performance analysis of multiple bus interconnection networks with hierarchical requesting model,"IEEE Trans. Comput., vol. 40, no. 7, pp. 834-842, July 1991.
[7] Q. Yang and S. G. Zaky, "Communication performance in multiple-bus systems,"IEEE Trans. Comput., vol. 37, no. 7, pp. 848-853, July 1988.
[8] S. S. Thakkar, P. R. Gifford, and G. F. Fieland, "The balance multiprocessor system,"IEEE Micro, pp. 57-69, Feb. 1988.
[9] T. Lovett and S. S. Thakkar, "The symmetry multiprocessor system," inProc. 1988 Int. Conf. Parallel Processing, 1988, pp. 303-310.
[10] Q. Yang and L. N. Bhuyan, "Analysis of packet-switched multiple-bus multiprocessor systems,"IEEE Trans. Comput., vol. 40, no. 3, pp. 352-357, Mar. 1991.
[11] Laxmi N. Bhuyan, "An analysis of processor-memory interconnection networks,"IEEE Trans. Comput., vol. C-34, no. 3, pp. 279-283, Mar. 1985.
[12] D. P. Bandarkar, "Analysis of memory interference in multiprocessors,"IEEE Trans. Comput., vol. C-24, no. 7, pp. 897-908, Sept. 1975.
[13] D.W.L. Yen, J. H. Patel and E. S. Davidson, "Memory interference in synchronous multiprocessor systems,"IEEE Trans. Comput., vol. C-31, no. 11, pp. 1116-1121, Nov. 1982.
[14] S. Wu and M. T. Liu, "A cluster structure as an interconnection network for large multimicrocomputer systems,"IEEE Trans. Comput., vol. C-30, pp. 254-264, Apr. 1981.
[15] D. P. Agrawal and I. O. Mahgoub, "Performance analysis of cluster based supersystems," inProc. First Int. Conf. Supercomput. Syst., Dec. 16-20, 1985, pp. 593-602.
[16] "Analysis of a class of cluster-based multiprocessor systems,"Inform. Sci., An Int. J., pp. 85-105, Oct. 1987.
[17] I. O. Mahgoub and A. K. Elmagarmid, "Performance analysis of a generalized class ofm-level hierarchical multiprocessor systems,"IEEE Trans. Parallel Distrib. Syst., vol. 3, no. 2, pp. 129-138, Mar. 1992.
[18] S. P. Dandamudi and D. L. Eager, "Hierarchical interconnection networks for multicomputer systems,"IEEE Trans. Comput., vol. 39, no. 6, pp. 786-797, June 1990.
[19] K. Hwang and J. Ghosh, "Hypernet: A communication-efficient architecture for constructing massively parallel computers,"IEEE Trans. Comput., vol. C-36, pp. 1450-1466, Dec. 1987.
[20] M. K. Molloy,Fundamentals of Performance Modeling. New York: Macmillan, 1989.
[21] E. D. Lazawskaet al., Quantitative System Performance--Computer System Analysis Using Queueing Network Models. Englewood Cliffs, NJ: Prentice-Hall, 1984.
[22] Joseph Di Giacomo,Digital Bus Handbook. New York: McGraw-Hill, 1990, p. 2.2.
[23] G. Chiola, M. A. Marsan, and G. Balbo, "Product-form solution techniques for the performance analysis of multiple-bus multiprocessor systems with nonuniform memory references,"IEEE Trans. Comput., vol. 37, no. 5, pp. 532-540, May 1988.
[24] Y-C Liu and C-J Jou, "Effective memory bandwidth and processor blocking probability in multiple-bus systems,"IEEE Trans. Comput., vol. C-36, pp. 761-764, June 1987.
[25] D. Towsley, "Approximate models of multiple bus multiprocessor systems,"IEEE Trans. Comput., vol. C-35, no. 3, pp. 220-228, Mar. 1986.
[26] T. N. Mudge and H. B. Al-Sadoun, "A semi-Markov model for the performance of multiple-bus systems,"IEEE Trans. Comput., vol. C-34, pp. 934-942, Oct. 1985.
[27] K. B. Irani and I. H. Onyuksel, "A closed-form solution for the performance analysis of multiple-bus multiprocessor systems,"IEEE Trans. Comput., vol. C-33, no. 11, pp. 1004-1012, Nov. 1984.
[28] M. A. Marsan and M. Gerla, "Markov models for multiple bus multiprocessor systems,"IEEE Trans. Comput., vol. C-31, no. 3, pp. 239-248, Mar. 1982.

Index Terms:
system buses; multiprocessing systems; parallel architectures; performance evaluation; queueing theory; performance analysis; multilevel bus networks; hierarchical multiprocessors; bandwidth; fault tolerance; memory modules; connections; switches; partial multiple bus system; bus architecture; hierarchical multiprocessor design; cost-effectiveness; local computations; analytical models; simulation models; synchronous multilevel bus systems; asynchronous multilevel bus systems; hierarchical reference model; memory bandwidth; packet-switched networks; MVA algorithm; queueing networks.
Citation:
S.M. Mahmud, "Performance Analysis of Multilevel Bus Networks for Hierarchical Multiprocessors," IEEE Transactions on Computers, vol. 43, no. 7, pp. 789-805, July 1994, doi:10.1109/12.293258
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