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Design of CAECC - Cellular Automata Based Error Correcting Code
June 1994 (vol. 43 no. 6)
pp. 759-764

A new scheme for designing error detecting and error correcting codes around cellular automata (CA) is reported. A simple and efficient scheme for generating SEC-DED codes is presented which can also be extended for generating codes with higher distances. A CA-based hardware scheme for very fast decoding (and correcting) of the codewords is also reported.

[1] S. Wolfram, "Random sequence generation by cellular automata,"Advances Appl. Math., vol. 7, pp. 127-169, 1986.
[2] P.D. Hortensius, R.D. McLeod, and B.W. Podaima, "Cellular Automata Circuits for Built-In Self-Test,"IBM J. Research and Development, Vol. 34, No. 213, Mar./ May 1990, pp. 389-405.
[3] A. K. Das, A. Ganguly, A. Dasgupta, S. Bhawmik, and P. Pal Chaudhuri, "Efficient characterization of cellular automata,"IEE Proc., vol. 137, Pt. E, no. 1, pp. 81-87, Jan. 1990.
[4] T.R.N. Rao and F. Fujawara,Error Control Codes for Computer Systems, Prentice Hall, 1989.
[5] E. Fujiwara and D. K. Pradhan, "Error-control coding in computers,"IEEE Comput. Mag., vol. 23, pp. 63-72, July 1990.
[6] W. W. Peterson and E. J. Weldon,Error Correcting Codes. Cambridge, MA: M.I.T. Press, 1972.
[7] H. Okano and H. Imai, "A construction method of high-speed decoders using ROM's for Bose-Chaudhuri-Hocquenghem and Reed-Solomon codes,"IEEE Trans. Comput., vol. C-36, pp. 1165-1171, 1987.
[8] K. Y. Liu, "Architecture design for VLSI design of RS decoders,"IEEE Trans. Comput., vol. C-33, Feb. 1984.
[9] A. K. Das, S. Saha, A. Roy Chowdhury, S. Misra, and P. Pal Chaudhuri, "Signature analyzer based on additive-cellular automata," inProc. 20th Fault Tolerant Computing Syst., pp. 265-272, U.K., June 1990.
[10] S. Misra, A. K. Das, D. Roy Chowdhury, and P. Pal Chaudhry, "Cellular automata--Theory and applications,"JIETE, vol. 36, nos. 3 and 4, pp. 251-259, 1990.
[11] G. C. Clark and J. B. Cain,Error-Correcting Coding for Digital Communications. New York: Plenum, 1981.
[12] S. Lin and D. J. Costello,Error Control Coding. Englewood Cliffs, NJ: Prentice-Hall, 1983.
[13] R. E. Blahut,Theory and Practice of Error Control Codes. Reading, MA: Addison-Wesley, 1984.
[14] D. Roy Chowdhury, S. Basu, I. Sen Gupta, and P. Pal Chaudhury, "Encoding and decoding of error correcting codes using cellular automata," presented at VLSI Design '92, Bangalore, India, Jan. 1992.
[15] D. K. Pradhan and S. K. Gupta, "A new framework for designing and analyzing BIST techniques and zero aliasing compression,"IEEE Trans. Comput., vol. 40, pp. 743-763, June 1991.
[16] K. N. Levitt and W. H. Kautz, "Cellular arrays for the parallel implementation of binary error-correcting codes,"IEEE Trans. Info. Theory. vol. IT-15, pp. 597-607, Sept. 1969.

Index Terms:
cellular automata; error detection codes; error correction codes; cellular automata based error correcting code; error detecting codes; SEC-DED codes; codewords.
Citation:
D. Roy Chowdhury, S. Basu, I. Sen Gupta, P. Pal Chaudhuri, "Design of CAECC - Cellular Automata Based Error Correcting Code," IEEE Transactions on Computers, vol. 43, no. 6, pp. 759-764, June 1994, doi:10.1109/12.286310
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