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Y.Y. Chen, S.J. Upadhyaya, "Modeling the Reliability of a Class of FaultTolerant VLSI/WSI Systems Based on MultipleLevel Redundancy," IEEE Transactions on Computers, vol. 43, no. 6, pp. 737748, June, 1994.  
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@article{ 10.1109/12.286306, author = {Y.Y. Chen and S.J. Upadhyaya}, title = {Modeling the Reliability of a Class of FaultTolerant VLSI/WSI Systems Based on MultipleLevel Redundancy}, journal ={IEEE Transactions on Computers}, volume = {43}, number = {6}, issn = {00189340}, year = {1994}, pages = {737748}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.286306}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Modeling the Reliability of a Class of FaultTolerant VLSI/WSI Systems Based on MultipleLevel Redundancy IS  6 SN  00189340 SP737 EP748 EPD  737748 A1  Y.Y. Chen, A1  S.J. Upadhyaya, PY  1994 KW  redundancy; VLSI; circuit reliability; logic testing; logic arrays; reliability theory; faulttolerant VLSI/WSI systems; multiplelevel redundancy; faulttolerant Very Large Scale Integration; large area array processors; residual redundancy; operational reliability; reliability; area prediction models; Markov model; yield. VL  43 JA  IEEE Transactions on Computers ER   
A class of faulttolerant Very Large Scale Integration (VLSI) and Wafer Scale Integration (WSI) schemes, called the multiplelevel redundancy, which incorporates both hierarchical and element level redundancy has been proposed for the design of high yield and high reliability large area array processors. The residual redundancy left unused after successfully reconfiguring and eliminating the manufacturing defects can be used to improve the operational reliability of a system. Since existing techniques for the analysis of the effect of residual redundancy on reliability improvement are not applicable, we present a new hierarchical model to estimate the reliability of the systems designed by our approach. Our model emphasizes the effect of support circuit (interconnection) failures on system reliability, leading to more accurate analysis. We discuss two area prediction models, one based on the regular WSI process, another based on the advanced WSI process, to estimate the arearelated parameters. This analysis gives an insight into the practical implementations of faulttolerant schemes in VLSI/WSI technology. Results of a computer experiment conducted to validate our models are also discussed.
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