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Hypergraph Coloring and Reconfigured RAM Testing
June 1994 (vol. 43 no. 6)
pp. 725-736

RAM decoders are designed with a view to minimize the overall silicon area and critical path lengths. This can result in designs in which-physically adjacent rows (and columns) are not logically adjacent. Even if physically adjacent rows (and columns) are logically adjacent, there are other issues that preclude the possibility of identical physical and logical addresses. State-of-the-art memory chips are designed with spare rows and spare columns for reconfiguration purposes. After a memory chip is reconfigured, physically adjacent cells may no longer have consecutive logical addresses. Test algorithms used at later stages for the detection of physical neighborhood pattern sensitive faults have to consider the fact that the address mapping of the memory chip is no longer available. We present test algorithms to detect 5-cell and 9-cell physical neighborhood pattern sensitive faults and arbitrary 3-coupling faults, even if the logical and physical addresses are different and the physical-to-logical address mapping is not available. These algorithms have test lengths of O(N[log/sub 3/N]/sup 4/) and O(N[log/sub 3/N]/sup 2/), respectively, for N-bit RAMs, and are especially suited for testing reconfigured DRAMs. They also detect other conventional faults such as stuck-at faults and decoder faults. These test algorithms are based on efficiently identifying all triplets of objects among a group of n objects. We formulated this triplet identification problem as a hypergraph coloring problem, and developed an efficient 3-coloring algorithm that colors the n vertices of a complete uniform hypergraph of rank 3 such that each edge of the hypergraph is trichromatically colored in at most [log/sub 3/n]/sup 2/ coloring steps.

[1] C. Berge,Graphs and Hypergraphs. New York: American Elsevier, 1976.
[2] M. M. Breuer and A. D. Friedman,Diagnosis and Reliable Design of Digital Systems. Potomac, MD: Computer Science Press, 1976.
[3] M. Canning, R. S. Dunn, and G. Jeansonne, "Active memory calls for discretion,"Electronics, vol. 40, pp. 143-154, Feb. 20, 1967.
[4] R. P. Cenker, D. G. Clemons, W. R. Huber, J. B. Petrizzi, F. J. Procyk, and G. M. Trout, "A fault-tolerant 64 K dynamic random access memory,"IEEE Trans. Electron Devices, vol. ED-26, pp. 853-860, June 1979.
[5] A. Chen, "Redundancy in LSI memory array,"IEEE J. Solid-State Circuits, vol. SC-4, pp. 291-293, Oct. 1969.
[6] W. Daehn and J. Gross, "A test generator IC for testing large CMOS-RAM's," inProc. Int. Test Conf., 1986, pp. 18-24.
[7] R. C. Evans, "Testing repairable RAM's and mostly good memories," inProc. Int. Test Conf., 1981, pp. 49-55.
[8] B. F. Fitzgerald and E. P. Thoma, "Circuit implementation of fusible redundant addresses of RAM's for productivity enhancement,"IBM J. Res. Develop., vol. 24, pp. 291-298, May 1980.
[9] M. Franklin, K.K. Saluja, and K. Kinoshita, "Built-In Self-Test Algorithm for Row/Column Pattern Sensitive Faults in RAMs,"IEEE J. Solid-State Circuits, Vol. 25, No. 2, Apr. 1990, pp. 514-524.
[10] C. Furnweger, "Dynamic interfacing, spare cells raise 16 K static RAM's speed and yield,"Electronics, vol. 55, pp. 121-124, Mar. 24, 1982.
[11] A.J. van de Goor and C.A. Verruijt, "An Overview of Deterministic Functional RAM Chip Testing,"ACM Computing Surveys, Vol. 22, No. 1, Mar. 1990, pp. 5-33.
[12] F. Harary, Graph Theory. Reading, MA: Addison-Wesley, 1969.
[13] J. P. Hayes, "Detection of pattern sensitive faults in random access memories,"IEEE Trans. Comput., vol. C-24, pp. 150-157, Feb. 1975.
[14] J. P. Hayes, "Testing memories for single-cell pattern-sensitive faults,"IEEE Trans. Comput., vol. C-29, pp. 249-254, Mar. 1980.
[15] D. Kantz, J. R. Goetz, R. Bender, M. Bahrings, J. Wawersig, W. Meyer, and W. Muller, "A 256 K DRAM with descrambled redundancy test capability,"IEEE J. Solid-State Circuits, vol. SC-19, pp. 596-602, Oct. 1984.
[16] T. Manoet al., A fault tolerant 256K RAM fabricated with molybdenum-polysilicon technology,"IEEE J. Solid-State Circuits, vol. SC-15, pp. 865-871, Oct. 1980.
[17] W. R. Moore, "A review of fault-tolerant techniques for the enhancement of integrated circuit yield,"Proc. IEEE, vol. PROC-74, pp. 684-698, May 1986.
[18] R. Nair, S. M. Thatte, and J. A. Abraham, "Efficient algorithms for testing semiconductor random access memories,"IEEE Trans. Comput., vol. C-27, pp. 572-576, June 1978.
[19] C. A. Papachristou and N. B. Sahgal, "An improved method for detecting functional faults in semiconductor random access memories,"IEEE Trans. Comput., vol. C-34, pp. 110-116, Feb. 1985.
[20] R. L. Petritz, "Current status of LSI technology,"IEEE J. Solid-State Circuits, vol. SC-2, pp. 130-147, Dec. 1967.
[21] K. K. Saluja and K. Kinoshita, "Test pattern generation for API faults in RAM,"IEEE Trans. Comput., vol. C-34, pp. 284-287, Mar. 1985.
[22] S. E. Schuster, "Multiple word/bit line redundancy for semiconductor memories,"IEEE J. Solid-State Circuits, vol. SC-13, pp. 698-703, Oct. 1978.
[23] S. C. Seth and K. Narayanaswamy, "A graph model for pattern-sensitive faults in random access memories,"IEEE Trans. Comput., vol. C-30, pp. 973-977, Dec. 1981.
[24] R. T. Smith, J. D. Chlipala, J. F. M. Bindels, R. G. Nelson, F. H. Fischer, and T.F. Mantz, "Laser programmable redundancy and yield improvement in a 64K DRAM,"IEEE J. Solid-State Circuits, vol. SC-16, no. 5, pp. 506-514, Oct. 1981.
[25] C. H. Stapper, "Block alignment: A method for increasing the yield of memory chips that are partially good," inDefect and Fault Tolerance in VLSI Systems, I. Koren, Ed. New York: Plenum Press, 1988.
[26] E. Tammaru and J. B. Angell, "Redundancy for LSI yield enhancement,"IEEE J. Solid State Circuits, vol. SC-2, no. 4, pp. 172-182, Dec. 1967.
[27] M. Tarr, D. Boudreau, and R. Murphy, "Defect analysis system speeds test and repair of redundant memories,"Electronics, vol. 57, pp. 175-179, Jan. 12, 1984.
[28] S. M. Thatte and J. A. Abraham, "Test generation for microprocessors,"IEEE Trans. Comput., vol. C-29, pp. 429-441, June 1980.
[29] A. Tuszynski, "Memory testing," inVLSI Testing, T. W. Williams, Ed. Amsterdam: Elsevier Science, 1986.

Index Terms:
graph colouring; redundancy; DRAM chips; integrated memory circuits; computational complexity; random-access storage; reconfigurable architectures; logic testing; hypergraph coloring; reconfigured RAM testing; RAM decoders; silicon area; critical path lengths; memory chips; physical neighborhood pattern sensitive faults; test algorithms; test lengths; reconfigured DRAMs; stuck-at faults; decoder faults.
M. Franklin, K.K. Saluja, "Hypergraph Coloring and Reconfigured RAM Testing," IEEE Transactions on Computers, vol. 43, no. 6, pp. 725-736, June 1994, doi:10.1109/12.286305
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