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A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits
June 1994 (vol. 43 no. 6)
pp. 687-697

We present a method to accelerate the search for the number of spares to be included in defect tolerant integrated circuits. Our method is obtained by bringing two modifications to a conventional evaluation method. The main motivations behind the development of this method are: the possibilities offered by the implementation of defect tolerance, the existence of many yield models, which may predict different results in terms of optimum number of spares, and the fact that some models are very compute intensive. The modeling methods leading to several usual yield models are briefly presented. We also present results showing that our method is valid for a wide range of parameters. However, this method can be applied to all yield models considered and it can significantly reduce the time spent in the search for the best possible reconfiguration strategies.

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Index Terms:
redundancy; circuit reliability; logic testing; integrated circuit manufacture; VLSI; defect-tolerant integrated circuits; defect tolerance; yield models; optimum number of spares; reconfiguration strategies; optimum redundancy.
Citation:
C. Thibeault, Y. Savaria, J.-L. Houle, "A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits," IEEE Transactions on Computers, vol. 43, no. 6, pp. 687-697, June 1994, doi:10.1109/12.286302
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