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Issue No.06 - June (1994 vol.43)
pp: 651-663
ABSTRACT
<p>The performance of the data cache in shared-memory multiprocessors has been shown to be different from that in uniprocessors. In particular, cache miss rates in multiprocessors do not show the sharp drop typical of uniprocessors when the size of the cache block increases. The resulting high cache miss rate is a cause of concern, since it can significantly limit the performance of multiprocessors. Some researchers have speculated that this effect is due to false sharing, the coherence transactions that result when different processors update different words of the same cache block in an interleaved fashion. While the analysis of six applications in the paper confirms that false sharing has a significant impact on the miss rate, the measurements also show that poor spatial locality among accesses to shared data has an even larger impact. To mitigate false sharing and to enhance spatial locality, we optimize the layout of shared data in cache blocks in a programmer-transparent manner. We show that this approach can reduce the number of misses on shared data by about 10% on average.</p>
INDEX TERMS
shared memory systems; buffer storage; performance evaluation; program compilers; false sharing; spatial locality; multiprocessor caches; data cache; shared-memory multiprocessors; cache miss rates; cache block; coherence transactions; interleaved fashion; shared data; programmer-transparent method.
CITATION
H.S. Lam, J. Torrellas, "False Sharing and Spatial Locality in Multiprocessor Caches", IEEE Transactions on Computers, vol.43, no. 6, pp. 651-663, June 1994, doi:10.1109/12.286299
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