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Comments on "Area-Time Optimal Adder Design"
April 1994 (vol. 43 no. 4)
pp. 507-512

A previous paper by Wei and Thompson (1990) defined a family of adders based on a modular design and presented an excellent systematic method of implementing a VLSI parallel adder using three types of component cells designed in static CMOS. Their approach to the adder design was based on the optimization of a formulated dynamic programming problem with respect to area and time. The authors first explicitly demonstrate the optimal 32-bit fast carry generator, described by Wei and Thompson, is incorrect. With suitable corrections, a correct 32-bit fast carry generator design is then presented. Next, BiCMOS technology is applied to implement the subcircuit of fast carry generator to accelerate the critical path. The authors show that the critical path delay of 16-bit, 32-bit and 66-bit adders is respectively shortened to 83.89%, 86.89% and 90.62% after introducing the BiCMOS drivers.

[1] B. W. Y. Wei and C. D. Thompson, "Area-time optimal adder design,"IEEE Trans. Comput., vol. 39, no. 5, May 1990.
[2] W. Fang, A. Brunnschweiler, and P. Ashburn, "An accurate analytical BiCMOS delay expression and its application in optimizing high-speed circuits,"IEEE J. Solid-State Circuits, vol. 27, no. 2, Feb. 1992.

Index Terms:
adders; carry logic; VLSI parallel adder; optimal 32-bit fast carry generator; fast carry generator; critical path delay; BiCMOS drivers; optimal adder design.
Citation:
Chien-In Henry Chen, A. Kumar, "Comments on "Area-Time Optimal Adder Design"," IEEE Transactions on Computers, vol. 43, no. 4, pp. 507-512, April 1994, doi:10.1109/12.278491
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