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A State Assignment Approach to Asynchronous CMOS Circuit Design
April 1994 (vol. 43 no. 4)
pp. 460-469

Present a new algorithm for state assignment in asynchronous circuits so that for each circuit state transition, only one (secondary) state variable switches. No intermediate unstable states are used. The resultant circuits operate at optimum speed in terms of the number of transitions made and use only static CMOS gates. By reducing the number of switching events per state transition, noise due to the switching events is reduced and dynamic power dissipation may also be reduced. This approach is suitable for asynchronous sequential circuits that are designed from flow tables or state transition diagrams. The proposed approach may also be useful for designing synchronous circuits, but explorations into the subject of clock power would be necessary to determine its usefulness.

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Index Terms:
state assignment; asynchronous sequential logic; sequential circuits; logic design; CMOS integrated circuits; integrated logic circuits; state assignment; asynchronous CMOS circuit design; asynchronous circuits; CMOS gates; switching events; asynchronous sequential circuits; flow tables; state transition diagrams.
Citation:
V. Kantabutra, A.G. Andreou, "A State Assignment Approach to Asynchronous CMOS Circuit Design," IEEE Transactions on Computers, vol. 43, no. 4, pp. 460-469, April 1994, doi:10.1109/12.278483
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