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Issue No.04 - April (1994 vol.43)
pp: 413-430
<p>Different multiple redundancy schemes for fault detection and correction in computational arrays are proposed and analyzed. The basic idea is to embed a logical array of nodes onto a processor/switch array such that d processors, 1/spl les/d/spl les/4, are dedicated to the computation associated with each node. The input to a node is directed to the d processors constituting that node, and the output of the node is computed by taking a majority vote among the outputs of the d processors. The proposed processor/switch array (PSVA) is versatile in the sense that it may be configured as a nonredundant system or as a system which supports double, triple or quadruple redundancy. It also allows for spares to be distributed in the PSVA in a way that permits spare sharing among nodes, thus enhancing the overall system reliability. In addition to choosing the required degree of redundancy, the flexibility of the PSVA architecture allows for the embedding of redundant arrays onto defective PSVA's and for run-time reconfiguration to avoid faulty processors and switches. Different embedding and reconfiguration algorithms are presented and analyzed using Markov chain techniques, using probability arguments, and via simulation.</p>
redundancy; parallel processing; fault tolerant computing; logic design; flexible redundancy; fault detection; correction; computational arrays; processor/switch array; redundancy; redundant arrays; reconfiguration algorithms; embedding; Markov chain techniques; probability arguments; faulty processors; fault tolerant arrays; reconfiguration; defect avoidance; fault masking.
J. Ramirez, R. Melhem, "Computational Arrays with Flexible Redundancy", IEEE Transactions on Computers, vol.43, no. 4, pp. 413-430, April 1994, doi:10.1109/12.278480
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