
This Article  
 
Share  
Bibliographic References  
Add to:  
Digg Furl Spurl Blink Simpy Del.icio.us Y!MyWeb  
Search  
 
ASCII Text  x  
P. Montuschi, L. Ciminiera, "OverRedundant Digit Sets and the Design of DigitByDigit Division Units," IEEE Transactions on Computers, vol. 43, no. 3, pp. 269277, March, 1994.  
BibTex  x  
@article{ 10.1109/12.272428, author = {P. Montuschi and L. Ciminiera}, title = {OverRedundant Digit Sets and the Design of DigitByDigit Division Units}, journal ={IEEE Transactions on Computers}, volume = {43}, number = {3}, issn = {00189340}, year = {1994}, pages = {269277}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.272428}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  OverRedundant Digit Sets and the Design of DigitByDigit Division Units IS  3 SN  00189340 SP269 EP277 EPD  269277 A1  P. Montuschi, A1  L. Ciminiera, PY  1994 KW  digital arithmetic; logic design; computer architecture; overredundant digit sets; digitbydigit division units; direct computation of division; remainder updating; prescaling; radixB division units. VL  43 JA  IEEE Transactions on Computers ER   
Overredundant digit sets are defined as those ranging from /spl minus/s to +s, with s/spl ges/B, B being the radix. This paper presents new techniques for the direct computation of division, that use an overredundant digit set for representing the quotient, instead of simply redundant ones used previously. In particular, general criteria for synthesizing the digit selection rules and remainder updating are given for any radix and index of redundancy. A methodology combining the use of overredundant digit sets with the prescaling of the divisor is also studied in order to achieve radixB division units with trivial digit selection functions. It is also shown, for the specific case of radix4 that using a prescaling slightly wider than in a radix4 unit by M.D. Ercegovac and T. Lang (1990) possible to avoid the digit selection table. The paper also presents a modified algorithm for onthefly conversion of the result into the irredundant form. The proposed methodology can be considered as an alternative to existing division techniques.
[1] D. E. Atkins, "Higherradix division using estimates of the divisor and partial remainders,"IEEE Trans. Comput., vol. C17, pp. 925934, Oct. 1968.
[2] A. Avizienis, "Signeddigit number representation for fast parallel arithmetic,"IRE Trans. Electron. Comput., vol. EC10, pp. 389400, Sept. 1961.
[3] W. S. Briggs and D. W. Matula, "Method and apparatus performing division using a rectangular aspect ratio multiplier," U.S. Patent No. 5046 038, Sept. 1991.
[4] L. Ciminiera and P. Montuschi, "Higher radix square rooting,"IEEE Trans. Comput., vol. 39, no. 10, pp. 12201231, Oct. 1990.
[5] M. D. Ercegovac, "A higherradix division with simple selection of quotient digits," inProc. 6th IEEE Symp. Comput. Arith., Aahrus, Denmark, June 1983, pp. 9498.
[6] M. D. Ercegovac and T. Lang, "Onthefly conversion of redundant into conventional representations,"IEEE Trans. Comput., vol. C36, no. 7, pp. 895897, July 1987.
[7] M. D. Ercegovac and T. Lang, "Online scheme for computing rotation factors,"J. Parallel and Distributed Computing, vol. 5, pp. 209227, 1988.
[8] M. D. Ercegovac and T. Lang, "Fast radix2 division with quotientdigit prediction,"J. VLSI Signal Processing, vol. 1, pp. 169180, 1989.
[9] M. D. Ercegovac and T. Lang, "Simple radix4 division with operands scaling,"IEEE Trans. Comput., vol. 39, pp. 12041208, Sept. 1990.
[10] M. D. Ercegovac and T. Lang, "Fast multiplication without carry propagate addition,"IEEE Trans. Comput., vol. 39, pp. 13851390, Nov. 1990.
[11] M. D. Ercegovac, T. Lang, and P. Montuschi, "Prescaling algorithms for veryhigh radix division," I.R. DAI/ARC 692, Dipartimento di Automatica e Informatica, Potitecnico di Torino, Torino, Italy, 1992.
[12] M. D. Ercegovac and T. Lang, "Digitrecurrence algorithms and implementations for division and square root," Internal Rep., Comput. Sci. Dep., UCLA, 1992.
[13] M. D. Ercegovac, T. Lang, and P. Montuschi, "Very high radix division with selection by rounding and prescaling, in11th IEEE Symp. Comput. Arithmetic, Windsor, ON, Canada, June 1993, pp. 112119.
[14] J. Fandrianto, "Algorithm for high speed shared radix4 division and radix4 squareroot," inProc. 8th IEEE Symp. Comput. Arithmetic, Como, Italy, May 1987, pp. 7379.
[15] J. Fandrianto, "Algorithm for high speed shared radix 8 division and radix 8 square root," inProc. 9th Symp. Comput. Arithmetic, Sept. 1989, pp. 6875.
[16] E. V. Khrisnamurthy, "On rangetransformation techniques for division,"IEEE Trans. Comput., vol. C19, pp. 227231, Mar. 1970.
[17] K. Hwang,Computer Arithmetic: Principles, Architecture, and Design. New York: Wiley, 1979.
[18] S. Kuninobu, T. Nishiyama, H. Edamatsu, T. Taniguchi, and N. Takagi, "Design of high speed MOS multiplier and divider using redundant binary representation," inProc. 8th IEEE Symp. Comput. Arithmetic, Como, Italy, May 1987, pp. 8086.
[19] D. W. Matula, "Design of a highly parallel floating point arithmetic unit," presented at theIEEE Symp. Combinatorial Optimizat. Sci. and Technol. (COST), at RUTCOR/DIMACS, April 1991.
[20] D. W. Ruck, S. K. Rogers, M. Kabrinsky, M. E. Oxley, and B. W. Sutter, "The multilayer perceptron as an approximation to a Bayes optimal discriminant function,"IEEE Trans. Neural Networks, vol. 1, no. 4, pp. 296298, Dec. 1990.
[21] P. Montuschi and M. Mezzalama, "Survey of square rooting algorithms,"IEE Proc., pt. E, vol. 137, pp. 3140, Jan. 1990.
[22] P. Montuschi and L. Ciminiera, "Designing digitbydigit division units with overredundant digit sets," I.R. DAI/ARC 1392, Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy.
[23] P. Montuschi and L. Ciminiera, "Design of a radix 4 division unit with simple selection table,"IEEE Trans. Comput., vol. 42, pp. 239246, Feb. 1993.
[24] J. E. Robertson, "A new class of digital division methods,"IRE Trans. Electron. Comput., vol. EC7, pp. 218222, Sept. 1958.
[25] A. Svoboda, "An algorithm for division,"Inform. Processing Math., vol. 9, pp. 2532, 1963.
[26] G. S. Taylor, "Radix 16 SRT dividers with overlapped quotient selection stages," inProc. 7th IEEE Symp. Comput. Arithmetic, Urbana, IL, June 1985, pp. 6471.
[27] P. K.G. Tu "Online arithmetic algorithms for efficient implementation," Ph.D. dissertation, Comput. Sci. Dep., U.C.L.A., CSD900029, Sept. 1990.
[28] M. J. Flynn and S. Waser,Introduction to Arithmetic for Digital Systems Designers. CBS College Publishing, 1982, pp. 215222.
[29] T. E. Williams and M. Horowitz, "SRT division diagrams and their usage in designing custom integrated circuits for division," Tech. Rep. No. CSLTR87326, Ctr. for Integrated Syst., Stanford Univ., Stanford, CA.
[30] J.B. Wilson and R. S. Ledley, "An algorithm for rapid binary division,"IRE Trans. Electron. Comput., vol. EC10, pp. 662670, Dec. 1961.
[31] S. Winograd, "On the time required for binary addition,"J. ACM, vol. 12, pp. 277285, 1965.
[32] J. H. Zurawski and J. B. Gosling, "Design of a highspeed square root multiply and divide unit,"IEEE Trans. Comput., vol. C36, pp. 1323, Jan. 1987.