This Article 
 Bibliographic References 
 Add to: 
High-Performance 3-1 Interlock Collapsing ALU's
March 1994 (vol. 43 no. 3)
pp. 257-268

A high-performance 3-1 interlock collapsing ALU, i.e., an ALU that allows the execution of most execution interlocks in a single machine cycle, is presented. We focus on reducing the Boolean equations describing the device and the incorporation of new mechanisms in the interlock collapsing ALU design. In particular, we focus on the reduction of the critical path, regarding delay, for the interlock collapsing ALU implementation. It is shown that the delay associated with the implementation of the proposed device, in terms of logic stages, assuming a commonly available CMOS technology, is equivalent to the number of logic stages required for the implementation of a 3-1 binary adder. The resulting implementation demonstrates that the proposed 3-1 interlock collapsing ALU can be designed to outperform existing schemes for interlock collapsing ALU's by a factor of at least two. Finally, it is suggested that the proposed device can be used in the implementation of multiple instruction issuing machines, allowing the issuance and execution of interlocks in parallel and in a single machine cycle with no cycle time increases.

[1] S. Vassiliadis, J. Phillips, and B. Blaner, "Interlock collapsing ALU's,"IEEE Trans. Comput., vol. 42, no. 7, pp. 825-839, July 1992.
[2] P. M. Kogge,The Architecture of Pipelined Computers. New York: McGraw-Hill, 1981.
[3] R. D. Acosta, J. Kjelstrup, and H. C. Torng, "An instruction issuing approach to enhancing performance in multiple functional unit processors,"IEEE Trans. Comput., vol. C-35, pp. 815-828, Sept. 1986.
[4] N. P. Jouppi, "The nonuniform distribution of instruction-level and machine parallelism and its effect on performance,"IEEE Trans. Comput., vol. 38, no. 12, pp. 1645-1658, Dec. 1989.
[5] N.P. Jouppi and D.W. Wall, "Available Instruction-Level Parallelism for Superpipelined and Superscalar Machines,"Third Int'l Conf. Architectural Support for Programming Languages and Operating Systems, IEEE CS Press, Los Alamitos, Calif., Order No. 1936, 1989, pp. 272-282.
[6] R.R. Oehler and R.D. Groves, "IBM RISC System/6000 Processor Architecture,"IBM J. Research and Development, Vol. 34, No. 1, Jan. 1990, pp. 23-36.
[7] W. A. Wulf, "The WM computer architecture,"Comput. Architecture News, vol. 16, no. 1, pp. 70-84, Mar. 1988.
[8] W. A. Wulf and C. Y. Hitchcock, III, "Apparatus for reading to and writing from memory streams of data while concurrently executing a plurality of data processing operations," U.S. Patent No. 4819 155, Apr. 1989.
[9] N. Malik, R. Eickemeyer, and S. Vassiliadis, "Instruction-level parallelism for execution interlock collapsing,"Comput. Architecture News, vol. 20, no. 4, pp. 38-43, Sept. 1992.
[10] H. Ling, "High speed binary adder,"IBM J. Res. Develop., vol. 25, no. 3, pp. 156-166, May 1981.
[11] S. Vassiliadis, "A comparison between adders with new defined carries and traditional schemes for addition,"Int. J. Electron., vol. 64, no. 4, pp. 617-626, Apr. 1988.
[12] S. Vassiliadis, "Recursive equations for hardwired binary adders,"Int. J. Electron., vol. 67, no. 2, pp. 201-213, Aug. 1989.
[13] D. W. Ruck, S. K. Rogers, M. Kabrinsky, M. E. Oxley, and B. W. Sutter, "The multilayer perceptron as an approximation to a Bayes optimal discriminant function,"IEEE Trans. Neural Networks, vol. 1, no. 4, pp. 296-298, Dec. 1990.
[14] S. Vassiliadis, J. Phillips, and B. Blaner, "ICU design considerations," IBM Tech. Rep. TR01.C114, Endicott, NY, Oct. 1991, p. 22.
[15] Vassiliadis. S. and J. Phillips, "Interlock collapsing SCISM ALU design," IBM Tech. Rep. TR01.C115, Endicott, NY, Oct. 1991, p. 31.
[16] Vassiliadis. S. and J. Phillips, "Early SCISM ALU status determination," IBM Tech. Rep. TR01.C205, Endicott, NY, Dec. 1991, p. 21.
[17] Vassiliadis. S. and J. Phillips, "Result equal zero predictor for 3-1 interlock collapsing ALU's ,"Int. J. Electron., vol. 75, no. 3, pp. 379-392, Sept. 1992.
[18] M. J. Flynn and S. Waser,Introduction to Arithmetic for Digital Systems Designers. CBS College Publishing, 1982, pp. 215-222.

Index Terms:
reduced instruction set computing; digital arithmetic; parallel architectures; 3-1 interlock collapsing ALU; execution interlocks; Boolean equations; critical path; delay; CMOS technology; multiple instruction issuing machines.
J. Phillips, S. Vassiliadis, "High-Performance 3-1 Interlock Collapsing ALU's," IEEE Transactions on Computers, vol. 43, no. 3, pp. 257-268, March 1994, doi:10.1109/12.272427
Usage of this product signifies your acceptance of the Terms of Use.