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Issue No.03 - March (1994 vol.43)
pp: 257-268
ABSTRACT
<p>A high-performance 3-1 interlock collapsing ALU, i.e., an ALU that allows the execution of most execution interlocks in a single machine cycle, is presented. We focus on reducing the Boolean equations describing the device and the incorporation of new mechanisms in the interlock collapsing ALU design. In particular, we focus on the reduction of the critical path, regarding delay, for the interlock collapsing ALU implementation. It is shown that the delay associated with the implementation of the proposed device, in terms of logic stages, assuming a commonly available CMOS technology, is equivalent to the number of logic stages required for the implementation of a 3-1 binary adder. The resulting implementation demonstrates that the proposed 3-1 interlock collapsing ALU can be designed to outperform existing schemes for interlock collapsing ALU's by a factor of at least two. Finally, it is suggested that the proposed device can be used in the implementation of multiple instruction issuing machines, allowing the issuance and execution of interlocks in parallel and in a single machine cycle with no cycle time increases.</p>
INDEX TERMS
reduced instruction set computing; digital arithmetic; parallel architectures; 3-1 interlock collapsing ALU; execution interlocks; Boolean equations; critical path; delay; CMOS technology; multiple instruction issuing machines.
CITATION
J. Phillips, S. Vassiliadis, "High-Performance 3-1 Interlock Collapsing ALU's", IEEE Transactions on Computers, vol.43, no. 3, pp. 257-268, March 1994, doi:10.1109/12.272427
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