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| Jianxun Ding, L.N. Bhuyan, "Finite Buffer Analysis of Multistage Interconnection Networks," IEEE Transactions on Computers, vol. 43, no. 2, pp. 243-247, February, 1994. | |||
| BibTex | x | ||
| @article{ 10.1109/12.262132, author = {Jianxun Ding and L.N. Bhuyan}, title = {Finite Buffer Analysis of Multistage Interconnection Networks}, journal ={IEEE Transactions on Computers}, volume = {43}, number = {2}, issn = {0018-9340}, year = {1994}, pages = {243-247}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.262132}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Finite Buffer Analysis of Multistage Interconnection Networks IS - 2 SN - 0018-9340 SP243 EP247 EPD - 243-247 A1 - Jianxun Ding, A1 - L.N. Bhuyan, PY - 1994 KW - multiprocessor interconnection networks; packet switching; finite buffer analysis; multistage interconnection networks; MIN; synchronous packet-switched mode; small clock periods; performance improvement; finite buffers; packet-switching performance. VL - 43 JA - IEEE Transactions on Computers ER - | |||
Proposes an analysis technique for a class of Multistage Interconnection Networks (MIN's) that have finite buffers at their switch inputs and operate in a synchronous packet-switched mode. The authors examine the issue of clock period in design and analysis of synchronous MIN's and propose a model based on small clock periods. Then they analyze their "small cycle" design and compare the results with those obtained from the standard "big cycle" model that is currently used. The significant performance improvement of their model is shown based on various clock width, data width, and buffer length.
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