
This Article  
 
Share  
Bibliographic References  
Add to:  
Digg Furl Spurl Blink Simpy Del.icio.us Y!MyWeb  
Search  
 
ASCII Text  x  
ShyueWin Wei, "A Systolic PowerSum Circuit for GF(2/sup m/)," IEEE Transactions on Computers, vol. 43, no. 2, pp. 226229, February, 1994.  
BibTex  x  
@article{ 10.1109/12.262128, author = {ShyueWin Wei}, title = {A Systolic PowerSum Circuit for GF(2/sup m/)}, journal ={IEEE Transactions on Computers}, volume = {43}, number = {2}, issn = {00189340}, year = {1994}, pages = {226229}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.262128}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  A Systolic PowerSum Circuit for GF(2/sup m/) IS  2 SN  00189340 SP226 EP229 EPD  226229 A1  ShyueWin Wei, PY  1994 KW  systolic arrays; error correction codes; logic gates; logic circuits; systolic powersum circuit; finite field; logical gates; powersum circuit; errorcorrecting codes; decoding. VL  43 JA  IEEE Transactions on Computers ER   
A systolic powersum circuit designed to perform AB/sup 2/+C computations in the finite field GF(2/sup m/) is presented, where A, B, and C are arbitrary elements of GF(2/sup m/). This new circuit is constructed by m/sup 2/ identical cells, each of which consists of three 2input AND logical gates, one 2input XOR gate, one 3input XOR gate, and ten latches. The AB/sup 2/+C computation is required in decoding many errorcorrecting codes. The paper shows that a decoder implemented using the new powersum circuit will have less complex circuitry and shorter decoding delay than one implemented using conventional productsum multipliers.
[1] R. E. Blahut,Theory and Practice of Error Control Codes. Reading, MA: AddisonWesley, 1983.
[2] A. M. Michelson and A. H. Levesque,ErrorControl Techniques for Digital Communication. New York: Wiley, 1985.
[3] S. Lin and D. J. Costellor, Jr.,Error Control Coding. Englewood Cliffs, NJ: PrenticeHall, 1983.
[4] H. M. Shao and I. S. Reed, "On the VLSI design of a pipeline ReedSolomon decoder using systolic arrays,"IEEE Trans. Comput., vol. C37, pp. 12731280, 1988.
[5] H. Okano and H. Imai, "A construction method of highspeed decoders using ROM's for BoseChaudhuriHocquenghem and ReedSolomon codes,"IEEE Trans. Comput., vol. C36, pp. 11651171, 1987.
[6] C.L. Wang and W.J. Bair, "A VLSI architecture for implementation of the decoder for binary BCH codes," inProc. Symp. Commun., TAiwan, Dec. 913, 1991, pp. 3640.
[7] S. W. Wei and C. H. Wei, "High speed decoder of ReedSolomon codes,"IEEE Trans. Commun., to appear.
[8] E. R. Berlekamp, "Bitserial ReedSolomon encoders,"IEEE Trans. Inform. Theory, vol. IT28, pp. 869874, Nov. 1982.
[9] C. C. Wang, T. K. Truong, H. M. Shao, L. J. Deutsch, J. K. Omura, and I. S. Reed, "VLSI architecture for computing multiplications and inverses in GF(2m),"IEEE Trans. Comput., vol. C34, pp. 709716, Aug. 1985.
[10] C.S. Yeh, S. Reed, and T. K. Truong, "Systolic multipliers for finite fields GF(2m),IEEE Trans. Comput., vol. C33, pp. 357360, 1984.
[11] B. A. Laws, Jr. and C. K. Rushforth, "A cellulararray multiplier for GF(2m),IEEE Trans. Comput., vol. C20, pp. 15731578, 1971.
[12] C.L. Wang and J.L. Lin, "Systolic array implementation of multipliers for finite fields GF(2m),"IEEE Trans. Circuits Syst., vol. 38, no. 7, pp. 796800, July 1988.