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A Systolic Power-Sum Circuit for GF(2/sup m/)
February 1994 (vol. 43 no. 2)
pp. 226-229

A systolic power-sum circuit designed to perform AB/sup 2/+C computations in the finite field GF(2/sup m/) is presented, where A, B, and C are arbitrary elements of GF(2/sup m/). This new circuit is constructed by m/sup 2/ identical cells, each of which consists of three 2-input AND logical gates, one 2-input XOR gate, one 3-input XOR gate, and ten latches. The AB/sup 2/+C computation is required in decoding many error-correcting codes. The paper shows that a decoder implemented using the new power-sum circuit will have less complex circuitry and shorter decoding delay than one implemented using conventional product-sum multipliers.

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Index Terms:
systolic arrays; error correction codes; logic gates; logic circuits; systolic power-sum circuit; finite field; logical gates; power-sum circuit; error-correcting codes; decoding.
Citation:
Shyue-Win Wei, "A Systolic Power-Sum Circuit for GF(2/sup m/)," IEEE Transactions on Computers, vol. 43, no. 2, pp. 226-229, Feb. 1994, doi:10.1109/12.262128
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