This Article 
 Bibliographic References 
 Add to: 
Compressed Tree Machines
February 1994 (vol. 43 no. 2)
pp. 222-225

A modified tree architecture called the compressed tree machine is proposed, and it is shown the compressed tree machine can be an alternative to the conventional tree machine.

[1] S. G. Akl,Parallel Sorting Algorithms. Orlando, FL: Academic, 1985.
[2] Selim G. Akl,The Design and Analysis of Parallel Algorithms. Englewood Cliffs, NJ: Prentice-Hall, 1989.
[3] J. L. Bently and H.-T. Kung, "A tree machine for searching problems," inProc. IEEE Int. Conf. Parallel Processing, pp. 257-266, 1979.
[4] S. N. Bhatt and F. T. Leighton, "A framework for solving VLSI graph layout problems,"J. of Comput. Syst. Sci., vol. 28, no. 2, pp. 300-343, 1984.
[5] S. N. Bhatt and C. E. Leiserson, "Minimizing the longest edge in a VLSI layout," Laboratory for Computer Science, MIT, Cambridge, MS, 1981 (unpublished memorandum).
[6] S. N. Bhatt and C. E. Leiserson, "How to assemble tree machines," inProc. 14th Annual ACM Symp. Theory Computing, pp. 77-84, 1982.
[7] R. P. Brent and H.-T. Kung, "On the area of binary tree layouts,"Informat. Processing Lett., vol. 11, no. 1, pp. 44-46, 1980.
[8] S. A. Browning, "The tree machine: A highly concurrent computing environment," Ph.D. dissertation, California Instit. of Technol., 1980.
[9] P. Czerwinski and V. Ramachandran, "Optimal VLSI graph embedding in variable aspect ratio rectangles,"Algorithmica, vol. 3, pp. 487-510, 1988.
[10] E. Dekel and S. Sahni, "Binary trees and parallel scheduling,"IEEE Trans. Comput., vol. C-32, pp. 307-315, 1983.
[11] M. J. Fischer and M. S. Paterson, "Optimal tree layout," inProc. 12th Annual ACM Symp. Theory Comput., pp. 177-189, 1980.
[12] E. Horowize and A. Zorat, "Divide-and-conquer for parallel processing,"IEEE Trans. Comput., vol. C-32, pp. 582-585, 1983.
[13] C. E. Leiserson, "Area-efficient graph layouts (for VLSI)," inProc, 21st Annual IEEE Symp. Foundations Comp. Sci., pp. 270-281, 1980.
[14] R. J. Lipton and J. Valdes, "Census functions: A approach to VLSI upper bounds," inProc, 22nd Annual IEEE Symp. Foundations Comp. Sci., pp. 13-22, 1981.
[15] C. Mead and L. Conway,Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980, pp. 150-152.
[16] M. S. Paterson, W. L. Ruzzo, and L. Snyder, "Bounds on minimax edge length for complete binary trees," inProc. 13th Annu. ACM Symp. Theory Comput., 1981, pp. 293-299.
[17] W. L. Ruzzo and L. Snyder, "Minimum edge length planar embeddings of trees," inVLSI Syst. and Computations, Kung, Sproull, and Steele, Eds., pp. 119-123, 1981.
[18] S. W. Song, "A highly concurrent tree machine for database applications," inProc. IEEE. Int. Conf. Parallel Processing, pp. 259-268, 1980.
[19] Q.F. Stout, "Sorting, merging, selecting and filtering on tree and pyramid machines," inProc. IEEE Int. Conf. Parallel Processing, pp. 214-221, 1983.
[20] C. D. Thompson, "Area-time complexity for VLSI," inProc. Eleventh Annu. ACM Symp. Theory Comput., 1979, pp. 81-88.
[21] C. D. Thompson, "A complexity theory for VLSI," Ph.D. dissertation, Dep. Comput. Sci., Carnegie Mellon Univ., 1980.
[22] J. D. Ullman,Computational Aspects of VLSI. Rockville, Md: Computer Science, 1984.

Index Terms:
parallel architectures; trees (mathematics); multiprocessor interconnection networks; modified tree architecture; compressed tree machine; parallel computer architecture; VLSI layout; tree structure; cost/performance trade-off; parallel processing; multiprocessor parallel computer.
Si-Qing Zheng, "Compressed Tree Machines," IEEE Transactions on Computers, vol. 43, no. 2, pp. 222-225, Feb. 1994, doi:10.1109/12.262127
Usage of this product signifies your acceptance of the Terms of Use.