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Gueesang Lee, M.J. Irwin, R.M. Owens, "Polynomial Time Testability of Circuits Generated by Input Decomposition," IEEE Transactions on Computers, vol. 43, no. 2, pp. 201210, February, 1994.  
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@article{ 10.1109/12.262124, author = {Gueesang Lee and M.J. Irwin and R.M. Owens}, title = {Polynomial Time Testability of Circuits Generated by Input Decomposition}, journal ={IEEE Transactions on Computers}, volume = {43}, number = {2}, issn = {00189340}, year = {1994}, pages = {201210}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.262124}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Polynomial Time Testability of Circuits Generated by Input Decomposition IS  2 SN  00189340 SP201 EP210 EPD  201210 A1  Gueesang Lee, A1  M.J. Irwin, A1  R.M. Owens, PY  1994 KW  combinatorial circuits; logic CAD; logic testing; testability; polynomial time; combinational circuits; input decomposition; logic synthesis tool; complexity; fault detection problem; stuckat fault; test generation. VL  43 JA  IEEE Transactions on Computers ER   
Considers polynomial time testability of combinational circuits generated by input decomposition, especially those generated by the logic synthesis tool FACTOR. First, the complexity of the fault detection problem in this class of circuits is explored using a stuckat fault model. An O(2/sup k/m) algorithm for detecting a single stuckat fault is given that is faster than the O(16/sup k/m), previously reported best algorithm proposed by Fujiwara(1990), where k is the number of inputs in a subcircuit and m the number of signal lines in the circuit. Efficient, polynomial time algorithms are described for generating a test set for all single stuckat faults in the circuit. The basic strategy is to eliminate backtracks during line justification by constructing tables or vector sets in each subcircuit, which makes the fault propagation procedure very simple and eventually results in an efficient test generation procedure. This presentation of efficient polynomial time test generation algorithms for FACTORgenerated circuits is important, since it shows that it is possible to synthesize circuits that are optimized for area and are polynomial time testable at the same time.
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