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Exploiting Instruction-Level Parallelism for Integrated Control-Flow Monitoring
February 1994 (vol. 43 no. 2)
pp. 129-140

Computer architectures are using increased degrees of instruction-level machine parallelism to achieve higher performance, e.g., superpipelined, superscalar and very long instruction word (VLIW) processors. Full utilization of such machine parallelism is difficult to achieve and sustain, resulting in the occurrence of idle resources at run time. This work explores the use of such idle resources for concurrent error detection in processors employing instruction-level machine parallelism. The Multiflow TRACE 14/300 processor, a VLIW machine, is chosen as an experimental vehicle. Experiments indicate that significant idle resources are likely to exist across a wide range of scientific applications for the TRACE 14/300. A methodology is presented for detecting transient control-flow errors, called available resource-driven control-flow monitoring (ARC), whose resource use can be tailored to the existence of idle resources in the processor. Results of applying ARC to the Multiflow TRACE 14/300 processor show that <99% of control-flow errors are detected with negligible performance overhead. These results demonstrate that ARC is highly effective in using the idle resources of a processor to achieve concurrent error detection at a very low cost.

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Index Terms:
parallel architectures; error detection; fault tolerant computing; instruction-level parallelism; control-flow monitoring; machine parallelism; idle resources; concurrent error detection; Multiflow TRACE 14/300 processor; TRACE 14/300; available resource-driven control-flow monitoring.
Citation:
M.A. Schuette, J.P. Shen, "Exploiting Instruction-Level Parallelism for Integrated Control-Flow Monitoring," IEEE Transactions on Computers, vol. 43, no. 2, pp. 129-140, Feb. 1994, doi:10.1109/12.262118
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