This Article 
 Bibliographic References 
 Add to: 
Exploiting Instruction-Level Parallelism for Integrated Control-Flow Monitoring
February 1994 (vol. 43 no. 2)
pp. 129-140

Computer architectures are using increased degrees of instruction-level machine parallelism to achieve higher performance, e.g., superpipelined, superscalar and very long instruction word (VLIW) processors. Full utilization of such machine parallelism is difficult to achieve and sustain, resulting in the occurrence of idle resources at run time. This work explores the use of such idle resources for concurrent error detection in processors employing instruction-level machine parallelism. The Multiflow TRACE 14/300 processor, a VLIW machine, is chosen as an experimental vehicle. Experiments indicate that significant idle resources are likely to exist across a wide range of scientific applications for the TRACE 14/300. A methodology is presented for detecting transient control-flow errors, called available resource-driven control-flow monitoring (ARC), whose resource use can be tailored to the existence of idle resources in the processor. Results of applying ARC to the Multiflow TRACE 14/300 processor show that <99% of control-flow errors are detected with negligible performance overhead. These results demonstrate that ARC is highly effective in using the idle resources of a processor to achieve concurrent error detection at a very low cost.

[1] A. L. Hopkins, Jr.,et al., "FTMP--A highly reliable fault-tolerant multiprocessor for aircraft," InProc. IEEE, vol. 66, pp. 1221-1239, Oct. 1978.
[2] A. Bashteen, I. Lui, and J. Mullan, "A superpipeline approach to the MIPS architecture." inCompCon '91, Feb. 1991, pp. 8-12.
[3] L. Chen and A. Avizienis, "N-version programming: A fault-tolerance approach to reliability of software operation," inIEEE 8th FTCS, 1978, pp. 3-9.
[4] R. P. Colwell, W. E. Hall, C. S. Joshi, D. B. Papworth, P. K. Rodman, and J. E. Tomes, "Architecture and implementation of a VLIW supercomputer," inSupercomputing '90, 1990, pp. 910-919.
[5] Robert P. Colwell et al., "A VLIW Architecture for a Trace Scheduling Compiler,"Proc. Second Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS II), Computer Society Press, Los Alamitos, Calif., No. 805 (microfiche), Oct. 1987, pp. 180-192.
[6] A. Ersoz, D. M. Andrews, and E. J. McClusky, "The watchdog task; Concurrent error detection using assertions," Tech. Rep., Stanford Univ., July 1985.
[7] J.-C. Fabre, Y. Deswarte, J-C. Laprie, and D. Powell, "Saturation: Reduced idleness for improved fault-tolerance," inIEEE 18th FTCS, June 1988, pp. 200-205.
[8] J. A. Fisher, "Trace scheduling: A technique for global microcode compaction,"IEEE Trans. Comput., vol. C-30, pp. 478-490, July 1981.
[9] J. A. Fisher, "Very long instruction word architectures and the ELI-512," inProc. 10th Annu. Int. Symp. Comput. Architecture, ACM-SIGARCH and the IEEE Computer Society, June 1983, pp. 140-150.
[10] J. F. Hart,et al., Computer Approximations. New York: John Wiley, 1968.
[11] IBM J. Res. Develop., vol. 34, Jan. 1990.
[12] M. Johnson,Superscalar Microprocessor Design. Englewood Cliffs, NJ: Prentice Hall, 1991.
[13] N. Jouppi, "The nonuniform distribution of instruction-level and machine parallelism and its effect on performance,"IEEE Trans. Comput., vol. 38, no. 12, pp. 1645-1658, Dec. 1989.
[14] M. Namjoo, "Techniques for concurrent testing of VLSI processor operation," inIEEE 12th FTCS, 1982, pp. 461-468.
[15] J. H. Patel and L. Y. Fung, "Concurrent error detection in ALU's by recomputing with shifted operands,"IEEE Trans. Comput., C-32, pp. 417-422, Apr. 1983.
[16] W. W. Peterson and E. J. Weldon, Jr.,Error Correcting Codes. Cambridge, MA: MIT Press, 1981.
[17] W. Press, B. Flannery, S. Teukolsky, and W. Vetterling,Numeric Recipes in C-The Art of Scientific Computing.Cambridge, UR: Cambridge University Press, 1988.
[18] M. Schuette and J. P. Shen, "Processor control flow monitoring using signatured instruction streams,"IEEE Trans. Comput., vol. C-36, pp. 264-276, Mar. 1987.
[19] M. A. Schuette and J. P. Shen, "An instruction-level performance analysis of the multiflow TRACE 14/300," inIEEE/ACM 24th Int. Symp. on Microarchitecture, June 1991, pp. 2-11.
[20] J. P. Shen and M. A. Schuette, "On-line monitoring using signatured instruction streams," inIEEE 13th ITC, Oct. 1983, pp. 275-282.
[21] G. Sohi,et al., "A study of time-redundant fault tolerance techniques for high-performance pipelined computers," inIEEE 19th FTCS, June 1989, pp. 436-443.
[22] T. Sridhar and S. M. Thatte, "Concurrent checking of program flow in VLSI processors." inIEEE 12th ITC, Nov. 1982, pp. 191-199.
[23] N. Warter and W. Hwu, "A software based approach to achieving optimal performance for signature control flow checking," inProc. 20th FTCS, 1990, pp. 442-449.
[24] K. Wilken and J. P. Shen, "Embedded signature monitoring: analysis and technique." inIEEE 17th ITC, Sept. 1987, pp. 324-333.
[25] K. D. Wilken and J. P. Shen, "Continuous signature monitoring: Efficient concurrent-detection of processor control errors,"Proc. Int. Test Conf., 1988, pp. 914-925.
[26] S. S. Yau and F. C. Chen, "An approach to concurrent control flow checking,"IEEE Trans. Sofrware Eng., vol. SE-6, no. 2, pp. 126-137, Mar. 1980.

Index Terms:
parallel architectures; error detection; fault tolerant computing; instruction-level parallelism; control-flow monitoring; machine parallelism; idle resources; concurrent error detection; Multiflow TRACE 14/300 processor; TRACE 14/300; available resource-driven control-flow monitoring.
M.A. Schuette, J.P. Shen, "Exploiting Instruction-Level Parallelism for Integrated Control-Flow Monitoring," IEEE Transactions on Computers, vol. 43, no. 2, pp. 129-140, Feb. 1994, doi:10.1109/12.262118
Usage of this product signifies your acceptance of the Terms of Use.