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N.M. Wigley, G.A. Jullien, D. Reaume, "Large Dynamic Range Computations Over Small Finite Rings," IEEE Transactions on Computers, vol. 43, no. 1, pp. 7886, January, 1994.  
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@article{ 10.1109/12.250611, author = {N.M. Wigley and G.A. Jullien and D. Reaume}, title = {Large Dynamic Range Computations Over Small Finite Rings}, journal ={IEEE Transactions on Computers}, volume = {43}, number = {1}, issn = {00189340}, year = {1994}, pages = {7886}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.250611}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  Large Dynamic Range Computations Over Small Finite Rings IS  1 SN  00189340 SP78 EP86 EPD  7886 A1  N.M. Wigley, A1  G.A. Jullien, A1  D. Reaume, PY  1994 KW  digital arithmetic; small finite rings; multivariate mapping strategy; Modulus Replication Residue Number System; Chinese Remainder Theorem; processor architecture; scaling strategy; complex arithmetic; dynamic logic; inner product computations; polynomial rings; quadratic residue rings; residue number systems; VLSI signal processors. VL  43 JA  IEEE Transactions on Computers ER   
Presents a new multivariate mapping strategy for the recently introduced Modulus Replication Residue Number System (MRRNS). This mapping allows computation over a large dynamic range using replications of extremely small rings. The technique maintains the useful features of the MRRNS, namely: ease of input coding; absence of a Chinese Remainder Theorem inverse mapping across the full dynamic range; replication of identical rings; and natural integration of complex data processing. The concepts are illustrated by a specific example of complex inner product processing associated with a radix4 decimation in time fast Fourier transform algorithm. A complete quantization analysis is performed and an efficient scaling strategy chosen based on the analysis. The example processor uses replications of three rings: modulo3, 5, and 7; the effective dynamic range is in excess of 32 b. The paper also includes verylargescaleintegration implementation strategies for the processor architecture that consists of arrays of massively parallel linear bitlevel pipelines.
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