This Article 
 Bibliographic References 
 Add to: 
Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders
January 1994 (vol. 43 no. 1)
pp. 68-77

Residue generator is an essential building block of encoding/decoding circuitry for arithmetic error detecting codes and binary-to-residue number system (RNS) converter. In either case, a residue generator is an overhead for a system and as such it should be built with minimum amount of hardware and should not compromise the speed of a system. Multioperand modular adder (MOMA) is a computational element used to implement various operations in digital signal processing systems using RNS. A comprehensive study of new residue generators and MOMA's is presented. The design methods given here take advantage of the periodicity of the series of powers of 2 taken module A (A is a module). Four design schemes of the n-input residue generators mod A, which are best suited for various pairs of n and A, are proposed. Their pipelined versions can be clocked with the cycle determined by the delay of a full-adder and a latch. A family of design methods for parallel and word-serial, using similar concepts, is also given. Both classes of circuits employ new highly-parallel schemes using carry-save adders with end-around carry and a minimal amount of ROM and are well-suited for VLSI implementation. They are faster and use less hardware than similar circuits known to date. One of the MOMA's can be used to build a high-speed residue-to-binary converter based on the Chinese remainder theorem.

[1] A. Avizienis, "A set of algorithms for a diagnosable arithmetic unit," Tech. Rep. 32-546, Jet Propulsion Lab., Calif. Inst. Technol., Pasadena, CA, Mar. 1964.
[2] A. Avizienis, "Arithmetic codes: Cost and effectiveness studies for applications in digital system design,"IEEE Trans. Comput., vol. C-20, pp. 1322-1331, Nov. 1971.
[3] J. F. Wakerly,Error Detecting Codes, Self-Checking Circuits and Applications. New York: North-Holland, 1978.
[4] S. J. Piestrak, "Self-testing checkers for arithmetic codes with any check baseA," inProc. 1991 Pacific Rim Int. Symp. Fault-Tolerant Syst., Kawasaki, Japan, Sept. 26-27, 1991, pp. 162-167.
[5] V. Piuri, M. Berzieri, A. Bisaschi, and A. Fabi, "Residue arithmetic for a fault-tolerant multiplier: The choice of the best triple of bases,"Microproc. and Microprogr., vol. 20, pp. 15-23, 1988.
[6] T. J. Slegel and R. J. Veracca, "Design and performance of the IBM Enterprise System/9000 Type 9121 vector facility,"IBM J. Res. Develop., vol. 35, pp. 367-381, May 1991.
[7] S. R. Barracloughet al., "The design and implementation of the IMS A110 image and signal processor," inProc. IEEE Custom Integr. Circuits Conf., 1989, pp. 24.5.1-24.5.4.
[8] M. A. Soderstrand, "A new hardware implementation of module adders for reside number systems," inProc. 26th Midwest Symp. Circuits Systems, 1983, pp. 412-415.
[9] N. S. Szabo and R. I. Tanaka,Residue Arithmetic and its Applications to Computer Technology. New York: McGraw-Hill, 1967.
[10] M. A. Soderstrand, W. K. Jenkins, G. A. Jullien, and F. J. Taylor, Eds.,Modern Applications of Residue Number System Arithmetic to Digital Signal Processing. New York: IEEE Press, 1986.
[11] W. K. Jenkins and B. J. Leon, "The use of residue number systems in the design of finite impulse response digital filters,"IEEE Trans. Circuits Syst., vol. CAS-24, pp. 191-201, Apr. 1977.
[12] M. Taheri, G. A. Jullien, and W. C. Miller, "High speed signal processing using systolic arrays over finite rings,"IEEE Trans. Select. Areas Commun., VLSI in Communications III, vol. 6, no. 3, pp. 504-512, Apr. 1988.
[13] C. N. Zhang, G. A. Jullien, and W. C. Miller, "Recursive reduction in finite ring computations," inProc. Conf. Rec. 23th Asilomar Conf. Circs., Systs, Comput., 1989, pp. 854-857.
[14] C. N. Zhang, G. A. Jullien, and W. C. Miller, "A neural-like network approach to finite ring computations,"IEEE Trans. Circuits Syst., vol. 37, pp. 1048-1052, Aug. 1990.
[15] R. M. Capocelli and R. Giancarlo, "Efficient VLSI networks for converting an integer from binary to residue numbers and vice versa,"IEEE Trans. Circuits Syst., vol. CAS-35, no. 11, pp. 1425-1430, 1988.
[16] G. Alia and E. Martinelli, "VLSI binary-residue converters for pipeline processing,"Comput. J., vol. 33, pp. 473-475, no. 5, 1990.
[17] K. Hwang,Computer Arithmetic: Principles, Architecture, and Design. New York: Wiley, 1979.
[18] C. N. Zhang, B. Shirazi, and D.Y.Y. Yun, "Parallel designs for Chinese remainder conversion," inProc. Int. Conf. Parallel Processing, Aug. 17-21, 1987, pp. 557-559.
[19] L. Skavantzos, "Design of multi-operand carry-save adders for arithmetic modulo (2n+ 1),"Electron. Lett., vol. 25, no. 17, pp. 1152-1153, Aug. 17, 1989.
[20] J. Fritz and R. Lackmann, "Optical Beam Induced Currents in MOS Transistors,"Microelectronic Engineering, Vol. 12, 1990, pp. 381-388.
[21] K. P. Lee, M. A. Bayoumi, and K. M. Elleithy, "A fast and flexible residue decoder based on the Chinese Remainder Theorem," inProc. ISCAS'89, 1989, pp. 200-203.
[22] K. M. Elleithy, M. A. Bayoumi, and K. P. Lee, "θ(lgN) architecture for RNS arithmetic decoding," inIEEE 9th Comput. Arith. Symp., 1989, pp. 202-209.
[23] I. S. Reedet al., "VLSI implementation of GSC architecture with a new ripple carry adder," inProc. ICCD'88, 1988, pp. 520-523.

Index Terms:
adders; digital arithmetic; residue generators; multioperand modular adders; carry-save adders; arithmetic error detecting codes; binary-to-residue number system; residue generator; Chinese remainder theorem; arithmetic codes; residue number system; residue arithmetic.
S.J. Piestrak, "Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders," IEEE Transactions on Computers, vol. 43, no. 1, pp. 68-77, Jan. 1994, doi:10.1109/12.250610
Usage of this product signifies your acceptance of the Terms of Use.