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S. Kawahito, M. Ishida, T. Nakamura, M. Kameyama, T. Higuchi, "HighSpeed AreaEfficient Multiplier Design Using MultipleValued CurrentMode Circuits," IEEE Transactions on Computers, vol. 43, no. 1, pp. 3442, January, 1994.  
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@article{ 10.1109/12.250607, author = {S. Kawahito and M. Ishida and T. Nakamura and M. Kameyama and T. Higuchi}, title = {HighSpeed AreaEfficient Multiplier Design Using MultipleValued CurrentMode Circuits}, journal ={IEEE Transactions on Computers}, volume = {43}, number = {1}, issn = {00189340}, year = {1994}, pages = {3442}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.250607}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  HighSpeed AreaEfficient Multiplier Design Using MultipleValued CurrentMode Circuits IS  1 SN  00189340 SP34 EP42 EPD  3442 A1  S. Kawahito, A1  M. Ishida, A1  T. Nakamura, A1  M. Kameyama, A1  T. Higuchi, PY  1994 KW  VLSI; multiplying circuits; multiplier design; multiplevalued currentmode circuits; VLSI; highspeed multiplier; carrypropagationfree addition trees; multiplevalued currentmode; carrypropagationfree addition; number representations; area efficient design; redundant number representations; tree structure. VL  43 JA  IEEE Transactions on Computers ER   
Presents a verylargescaleintegration (VLSI)oriented highspeed multiplier design method based on carrypropagationfree addition trees and a circuit technique, socalled multiplevalued currentmode (MVCM) circuits. The carrypropagationfree addition method uses a redundant digit set such as /spl lcub/0,1,2,3/spl rcub/ and /spl lcub/0,1,2,3,4/spl rcub/. The number representations using such redundant digit sets are called redundant positivedigit number representations. The carrypropagationfree addition is written by three steps, and the adder can be designed directly and efficiently from the algorithm using MVCM circuits. The designed multiplier internally using the MVCM parallel adder with the digit set /spl lcub/0,1,2,3/spl rcub/ in radix 2 has attractive features on speed, regularity of the structure, and reduced complexities of active elements and interconnections. A prototype CMOS integrated circuit of the MVCM parallel adder has been implemented, and its stable operation has been confirmed. Other possible schemes of multipliers with redundant digit sets using MVCM technology are discussed.
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