This Article 
 Bibliographic References 
 Add to: 
High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits
January 1994 (vol. 43 no. 1)
pp. 34-42

Presents a very-large-scale-integration (VLSI)-oriented high-speed multiplier design method based on carry-propagation-free addition trees and a circuit technique, so-called multiple-valued current-mode (MVCM) circuits. The carry-propagation-free addition method uses a redundant digit set such as /spl lcub/0,1,2,3/spl rcub/ and /spl lcub/0,1,2,3,4/spl rcub/. The number representations using such redundant digit sets are called redundant positive-digit number representations. The carry-propagation-free addition is written by three steps, and the adder can be designed directly and efficiently from the algorithm using MVCM circuits. The designed multiplier internally using the MVCM parallel adder with the digit set /spl lcub/0,1,2,3/spl rcub/ in radix 2 has attractive features on speed, regularity of the structure, and reduced complexities of active elements and interconnections. A prototype CMOS integrated circuit of the MVCM parallel adder has been implemented, and its stable operation has been confirmed. Other possible schemes of multipliers with redundant digit sets using MVCM technology are discussed.

[1] C. S. Wallace, "A suggestion for a fast multiplier,"IEEE Trans. Electron. Comput., vol. EC-13, pp. 14-17, Feb. 1964.
[2] L. Dadda, "Some schemes for parallel multipliers,"Alta Freq., vol. 34, pp. 349-356, Mar. 1965.
[3] L. Dadda, "On parallel digital multipliers,"Alta Freq., vol. 45, pp. 574-580, 1976.
[4] A. Avizienis, "Signed-digit number representations for fast parallel arithmetic,"IRE Trans. Elect. Comput., vol. EC-10, pp. 389-400, Sept. 1961.
[5] N. Takagi, H. Yasuura, and S. Yajima, "High-speed VLSI multiplication algorithm with a redundant binary addition tree,"IEEE Trans. Comput., vol. C-34, no. 9, pp. 789-796, Sept. 1985.
[6] J. E. Vuillemin, "A very fast multiplication algorithm for VLSI implementation,"Integration, VLSI J., vol. 1, pp. 39-52, Apr. 1983.
[7] E. E. Swartzlander, "Parallel counters,"IEEE Trans. Comput., vol. C-22, pp. 1021-1024, Nov. 1973.
[8] S. Kawahito, K. Mizuno, and T. Nakamura, "Multiple-valued current-mode arithmetic circuits based on redundant positive-digit number representations," inProc. Int. Symp. Multiple-Valued Logic, Victoria, Canada, May 1991, pp. 330-339.
[9] M. Kameyama and T. Higuchi, "Design of radix-4 signed-digit arithmetic circuits for digital filtering," inProc. Int. Symp. Multiple-Valued Logic, June 1980, pp. 272-277.
[10] S. Kawahito, M. Kameyama, T. Higuchi, and H. Yamada, "32×32 bit multiplier using multiple-valued MOS current-mode circuits,"IEEE J. Solid-State Circuits, vol. SC-23, pp. 124-132, Feb. 1988.
[11] M. Kameyama, S. Kawahito, and T. Higuchi, "A multiplier chip with multiple-valued bidirectional current-mode logic circuits,"IEEE Computer, vol. 21, pp. 43-56, Apr. 1988.
[12] L. P. Rubinfield, "A proof of the modified Booth's algorithm for multiplication,"IEEE Trans. Comput., vol. C-24, pp. 1014-1015, Oct. 1975.
[13] S. H. Unger, "Tree realizations of iterative circuits,"IEEE Trans. Comput., vol. C-26, pp. 365-383, Apr. 1977.
[14] K. Hwang,Computer Arithmetic: Principles, Architecture, and Design. New York: Wiley, 1979.
[15] R. K. Montoye, P. W. Cook, E. Hokenek, and R. P. Havreluk, "An 18 ns 56-bit multiply-adder circuit," inDig. Tech. Papers, Int. Solid-State Circuits Conf., WPM 3.4, Feb. 1990, pp. 46-47.
[16] P. J. Song and G. De Micheli, "Circuit and architecture trade-offs for high-speed multiplication,"IEEE J. Solid-State Circuits, vol. 26, pp. 1184-1198, Sept. 1991.
[17] S. Kawahito, M. Kameyama, and T. Higuchi, "Multiple-valued radix- 2 signed-digit arithmetic circuits for high-performance VLSI systems,"IEEE J. Solid-State Circuits, vol. SC-25, pp. 125-131, Feb. 1990.
[18] M. Santoro and M. Horowitz, "SPIM: A pipelined 64×64-bit iterative multiplier,"IEEE J. Solid-State Circuits, pp. 487-493, Apr. 1989.
[19] M. Mehta, V. Parmar, and E. Swartzlander, "High-speed multiplier design using multi-input counters and compressor circuits," inProc. Int. Symp. Comput. Arithmetic, 1991, pp. 43-50.

Index Terms:
VLSI; multiplying circuits; multiplier design; multiple-valued current-mode circuits; VLSI; high-speed multiplier; carry-propagation-free addition trees; multiple-valued current-mode; carry-propagation-free addition; number representations; area efficient design; redundant number representations; tree structure.
S. Kawahito, M. Ishida, T. Nakamura, M. Kameyama, T. Higuchi, "High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits," IEEE Transactions on Computers, vol. 43, no. 1, pp. 34-42, Jan. 1994, doi:10.1109/12.250607
Usage of this product signifies your acceptance of the Terms of Use.