Issue No.01 - January (1994 vol.43)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.250607
<p>Presents a very-large-scale-integration (VLSI)-oriented high-speed multiplier design method based on carry-propagation-free addition trees and a circuit technique, so-called multiple-valued current-mode (MVCM) circuits. The carry-propagation-free addition method uses a redundant digit set such as /spl lcub/0,1,2,3/spl rcub/ and /spl lcub/0,1,2,3,4/spl rcub/. The number representations using such redundant digit sets are called redundant positive-digit number representations. The carry-propagation-free addition is written by three steps, and the adder can be designed directly and efficiently from the algorithm using MVCM circuits. The designed multiplier internally using the MVCM parallel adder with the digit set /spl lcub/0,1,2,3/spl rcub/ in radix 2 has attractive features on speed, regularity of the structure, and reduced complexities of active elements and interconnections. A prototype CMOS integrated circuit of the MVCM parallel adder has been implemented, and its stable operation has been confirmed. Other possible schemes of multipliers with redundant digit sets using MVCM technology are discussed.</p>
VLSI; multiplying circuits; multiplier design; multiple-valued current-mode circuits; VLSI; high-speed multiplier; carry-propagation-free addition trees; multiple-valued current-mode; carry-propagation-free addition; number representations; area efficient design; redundant number representations; tree structure.
M. Ishida, T. Nakamura, M. Kameyama, T. Higuchi, "High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits", IEEE Transactions on Computers, vol.43, no. 1, pp. 34-42, January 1994, doi:10.1109/12.250607