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Recursive Pseudoexhaustive Test Pattern Generation
December 1993 (vol. 42 no. 12)
pp. 1517-1521

A recursive technique for generating exhaustive patterns is presented. The method is optimal, i.e., in one experiment it covers exhaustively every block of k adjacent inputs in the first 2/sup k/ vectors. Implementation methods based on characteristic functions of test vectors are provided. They include a parallel pattern generator employing an exclusive-or array, and two serial generators that can be easily adopted in a scan-based built-in self-test environment.

[1] M. Abramovici, M. A. Breuer, and A. D. Friedman,Digital Systems Testing and Testable Design. New York: Computer Science Press, 1990.
[2] S. B. Akers, "On the use of linear sums in exhaustive testing," inProc. FTCS'85, pp. 148-153.
[3] S. B. Akers, "A parity bit signature for exhaustive testing," inProc. ITC 1986, pp. 48-53.
[4] S. B. Akers and W. Jansz, "Test set embedding in a built-in self-test environment," inProc. ITC 1989, pp. 257-263.
[5] Z. Barzilai, D. Coppersmith, and A. L. Rosenberg, "Exhaustive generation of bit patterns with applications to VLSI self-testing,"IEEE Trans. Comput., vol. C-32, pp. 190-194, Feb. 1983.
[6] P. H. Bardell, W. H. McAnney, and J. Savir,Built-In Test for VLSI: Pseudorandom Techniques. New York: Wiley, 1987.
[7] A. K. Chandra, L. T. Kou, G. Markowsky, and S. Zaks, "On sets of Booleann-vectors with allk-projections surjective,"Acta Inform., vol. 20, pp. 103-111, 1983.
[8] C. L. Chen, "Exhaustive test pattern generation using cyclic codes,"IEEE Trans. Comput., vol. 37, pp. 225-228, Feb. 1988.
[9] B. I. Dervisogiu, "VLSI self-testing using exhaustive bit patterns," inProc. FTCS 1985, pp. 558-561.
[10] P. Golan, O. Novak, and J. Hlavicka, "Pseudoexhaustive test pattern generator with enhanced fault coverage,"IEEE Trans. Comput., vol. 37, pp. 496-500, Apr. 1988.
[11] H. Hiraishi, K. Kawahara, and S. Yajima, "Locally exhaustive testing of combinational circuits using linear logic circuits,"J. Inform. Processing, vol. 11, 3, pp. 191-198, 1988.
[12] H. Hollman, "Design of test sequences for VLSI self-testing using LFSR,"IEEE Trans. Inform. Theory, vol. 36, pp. 386-392, Mar. 1990.
[13] A. Lempel and M. Cohn, "Design of universal test sequences for VLSI,"IEEE Trans. Inform. Theory, vol. IT-31, no. 1, pp. 10-17, Jan. 1985.
[14] E. J. McCluskey and S. Bozorgui-Nesbat, "Design for autonomous test,"IEEE Trans. Circuits Syst., vol. CAS-28, pp. 1070-1079, Nov. 1981.
[15] E. J. McCluskey, "Verification testing-A pseudoexhaustive test technique,"IEEE Trans. Comput., vol. C-33, pp. 541-546, June 1984.
[16] G. Seroussi and N. H. Bshouty, "Vector sets for exhaustive testing of logic circuits,"IEEE Trans. Inform. Theory, vol. 34, pp. 513-522, May 1988.
[17] D. T. Tang and C.-L. Cheng, "Logic test pattern generation using linear codes,"IEEE Trans. Comput., vol. C-33, pp. 845-850, Sept. 1984.
[18] D. T. Tang and L. S. Woo, "Exhaustive test-pattern generation with constant weight vectors,"IEEE Trans. Comput., vol. C-32, pp. 1145-1150, Dec. 1983.
[19] L.-T. Wang and E. J. McCluskey, "Circuits for pseudoexhaustive test pattern generation,"IEEE Trans. Comput-Aided Design, vol. CAD-7, pp. 1068-1980, Oct. 1988.
[20] L.-T. Wang and E. J. McCluskey, "Linear feedback shift register design using cyclic codes,"IEEE Trans. Comput., vol. 37, pp. 1302-1306, Oct. 1988.

Index Terms:
built-in self test; logic testing; recursive pseudoexhaustive test pattern generation; characteristic functions; test vectors; parallel pattern generator; exclusive-or array; serial generators; scan-based built-in self-test.
Citation:
J. Rajski, J. Tyszer, "Recursive Pseudoexhaustive Test Pattern Generation," IEEE Transactions on Computers, vol. 42, no. 12, pp. 1517-1521, Dec. 1993, doi:10.1109/12.260644
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