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P. Mazumder, "Design of a FaultTolerant ThreeDimensional Dynamic RandomAccess Memory with OnChip ErrorCorrecting Circuit," IEEE Transactions on Computers, vol. 42, no. 12, pp. 14531468, December, 1993.  
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@article{ 10.1109/12.260635, author = {P. Mazumder}, title = {Design of a FaultTolerant ThreeDimensional Dynamic RandomAccess Memory with OnChip ErrorCorrecting Circuit}, journal ={IEEE Transactions on Computers}, volume = {42}, number = {12}, issn = {00189340}, year = {1993}, pages = {14531468}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.260635}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Design of a FaultTolerant ThreeDimensional Dynamic RandomAccess Memory with OnChip ErrorCorrecting Circuit IS  12 SN  00189340 SP1453 EP1468 EPD  14531468 A1  P. Mazumder, PY  1993 KW  DRAM chips; error correction codes; fault tolerant computing; faulttolerant threedimensional dynamic randomaccess memory; onchip errorcorrecting circuit; storage capacitors; plasma shorts; doublebit soft errors; memorycell upsets; errorcorrectingcode. VL  42 JA  IEEE Transactions on Computers ER   
Most currentgeneration multimegabit dynamic randomaccess memory (DRAM) chips use threedimensional storage capacitors where the charge is stored on a vertically integrated trenchtype structure and are highly vulnerable to alpha particles, which frequently create plasma shorts between two adjoining trench capacitors on the same word line, resulting in uncorrectable doublebit soft errors. The author presents a systematic study of softerror related problems and discusses methodologies for correcting singlebit and doublebit memorycell upsets by using onchip errorcorrectingcode (ECC) circuits. By modifying the product code, an effective coding scheme has been designed that can be integrated within a DRAM chip to correct doublebit errors. It is demonstrated that the reliability of a memory chip can be improved by several million times by integrating the proposed circuit. The area and timing overhead are calculated and compared with those of memory chips without any ECC and chips with singleerrorcorrecting (SEC) codes. The ability of the circuit to correct soft errors in the presence of multiplebit errors is analyzed.
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