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Design of a Fault-Tolerant Three-Dimensional Dynamic Random-Access Memory with On-Chip Error-Correcting Circuit
December 1993 (vol. 42 no. 12)
pp. 1453-1468

Most current-generation multimegabit dynamic random-access memory (DRAM) chips use three-dimensional storage capacitors where the charge is stored on a vertically integrated trench-type structure and are highly vulnerable to alpha particles, which frequently create plasma shorts between two adjoining trench capacitors on the same word line, resulting in uncorrectable double-bit soft errors. The author presents a systematic study of soft-error related problems and discusses methodologies for correcting single-bit and double-bit memory-cell upsets by using on-chip error-correcting-code (ECC) circuits. By modifying the product code, an effective coding scheme has been designed that can be integrated within a DRAM chip to correct double-bit errors. It is demonstrated that the reliability of a memory chip can be improved by several million times by integrating the proposed circuit. The area and timing overhead are calculated and compared with those of memory chips without any ECC and chips with single-error-correcting (SEC) codes. The ability of the circuit to correct soft errors in the presence of multiple-bit errors is analyzed.

[1] D. F. Barbe,Very Large Scale Integration: Fundamentals and Applications. Berlin: Springer-Verlag, 1980.
[2] L. L. Lewyn and J. D. Meindl, "Physical limits of VLSI dRAM's,IEEE J. Solid-State Circuits, vol. SC-20, pp. 231-241, Feb. 1985.
[3] J. Yamada, "Selector-line merged built-in ECC technique for DRAM's,"IEEE J. Solid-State Circuits, vol. SC-22, no. 5, pp. 868-873, Oct. 1987.
[4] A. H. Shahet al., "A 4-Mbit DRAM with trench-transistor cell,"IEEE J. Solid-State Circuits, vol. SC-21, pp. 618-627, Oct. 1986.
[5] T. Kagaet al., "A 4.2µm2half-VCCsheath-plate capacitor DRAM cell with self-aligned buried plate-wiring,"IEDM Dig., Oct. 1987, pp. 332-335.
[6] F. Horiguchiet al., "Process technologies for high-density, high-speed 16M-bit dynamic RAM," inProc. Int. Conf. Electronic Devices Manufacturing, Oct. 1987, pp. 324-327.
[7] P. Mazumder, J. H. Patel, and W. K. Fuchs, "Design and algorithms for parallel testing of random-access and content-addressable-memories,"Design Automation Conf., vol. 24, pp. 688-694, July 1987.
[8] Y. You and J.P. Hayes, "A Self-Testing Dynamic RAM Chip,"IEEE J. Solid-State Circuits, Vol. 20, No. 1, Feb. 1985, pp. 428-435.
[9] T. Sridhar, "A new parallel test approach for large memories," inProc. Int. Test Conf., 1985, pp. 462-470.
[10] A. Tuszynski, "Memory chip test economics," inProc. Int. Test Conf., 1986, pp. 190-194.
[11] P. Mazumder and J. H. Patel, "Parallel algorithms for parametric faults in DRAM," presented at 5th MIT Conf. Advanced Research in VLSI, Mar. 1988.
[12] J. S. Chern, P. Yang, P. Patnaik, and J. A. Seitchik, "Alpha-particle-induced charge transfer between closely spaced memory cells,"IEEE Trans. Electron Devices, vol. ED-33, pp. 822-834, June-1986.
[13] R. J. McPartland, "Circuit simulations of alpha-particle-induced soft errors in MOS dynamic RAM's,"IEEE J. Solid-State Circuits, vol. SC-16, pp. 31-34, Feb. 1981.
[14] T. C. May and M. H. Woods, "Alpha-particle-induced soft errors in dynamic memories,"IEEE Trans. Electron Devices, vol. ED-26, pp. 2-9, Jan. 1979.
[15] G. A. Sai-Halasz, M. R. Wordeman, and R. H. Dennard, "Alpha-particle-induced soft-error rate in VLSI circuits,"IEEE J. Solid-State Circuits, vol. SC-17, pp. 355-362, Apr. 1982.
[16] Meierenet al., "Measurements of alpha particle radioactivity in IC device packages," inProc. 1979 Int. Reliabil. Phys. Symp., 1979, pp. 13-21.
[17] D. C. Yaneyet al., "Alpha-particle-tracks in silicon and their effects on dynamic MOS RAM reliability,"IEEE Trans. Electron Devices, vol. ED-26, pp. 853-860, June 1979.
[18] T. Kubotaet al., "A new soft-error immune DRAM cell with a transistor on a lateral epitaxial silicon layer (TOLE cell)," inIEDM Dig., Oct. 1987, pp. 344-347.
[19] T. Toyabeet al., "A soft-error rate model for MOS dynamic RAM's,"IEEE J. Solid-State Circuits, vol. SC-17, pp. 362-367, Apr. 1982.
[20] K. Shimogashiet al., "An n-well CMOS dynamic RAM,"IEEE J. Solid-State Circuits, vol. SC-17, pp. 344-348, Apr. 1982.
[21] F. I. Osman, "Error-correction techniques for random-access memories,"IEEE J. Solid-State Circuits, vol. SC-17, pp. 877-881, Oct. 1982.
[22] P. Mazumder and J. H. Patel, "A novel fault-tolerant design of testable dynamic random-access memory," inProc. Int. Conf. Computer Design, Oct. 1987.
[23] W. W. Peterson and E. J. Weldon, inError Correcting Codes. Cambridge, MA: MIT Press, 1972.
[24] S. Lin,An Introduction to Error-Correcting Codes. Englewood Cliffs, NJ: Prentice-Hall, 1980.
[25] R. M. Tanner, "A recursive approach to low-complexity codes,"IEEE Trans. Inform. Theory, vol. IT-27, pp. 533-547, Sept. 1981.
[26] T. Yamada, H. Kotani, J. Matsushima, and M. Inoue, "A 4-Mbit DRAM with 16-bit concurrent ECC,"IEEE J. Solid-State Circuits, vol. SC-23, pp. 20-25, Feb. 1988.
[27] R. Carmichael,Introduction to the Theory of Groups of Finite Order. New York: Dover, 1956.
[28] R. M. Tanner, "A recursive approach to low-complexity codes,"IEEE Trans. Inform. Theory, vol. IT-27, pp. 533-547, Sept. 1981.
[29] P. Dembwski,Finite Geometries. Berlin: Springer, 1968.

Index Terms:
DRAM chips; error correction codes; fault tolerant computing; fault-tolerant three-dimensional dynamic random-access memory; on-chip error-correcting circuit; storage capacitors; plasma shorts; double-bit soft errors; memory-cell upsets; error-correcting-code.
Citation:
P. Mazumder, "Design of a Fault-Tolerant Three-Dimensional Dynamic Random-Access Memory with On-Chip Error-Correcting Circuit," IEEE Transactions on Computers, vol. 42, no. 12, pp. 1453-1468, Dec. 1993, doi:10.1109/12.260635
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