Issue No.12 - December (1993 vol.42)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.260632
<p>Introduces an innovative cache design for vector computers, called prime-mapped cache. By utilizing the special properties of a Mersenne prime, the new design does not increase the critical path length of a processor, nor does it increase the cache access time as compared to existing cache organizations. The prime-mapped cache minimizes cache miss ratio caused by line interferences that have been shown to be critical for numerical applications by previous investigators. With negligibly additional hardware cost, significant performance gains are obtained by adding the proposed cache memory to an existing vector computer. The performance of the design is studied analytically, using a generic vector computation model. The analytical model is validated through extensive simulation experiments. A performance analysis for various vector access patterns shows that the prime-mapped cache performs significantly better than conventional cache organizations in the vector processing environment. The performance gain will increase with the increase of the speed gap between processors and memories.</p>
buffer storage; memory architecture; vector processor systems; cache design; vector computers; prime-mapped cache; Mersenne prime; cache miss ratio; performance gains; speed gap; cache organizations.
Quing Yang, "Introducing a New Cache Design into Vector Computers", IEEE Transactions on Computers, vol.42, no. 12, pp. 1411-1424, December 1993, doi:10.1109/12.260632