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An Efficient Algorithm for Sequential Circuit Test Generation
November 1993 (vol. 42 no. 11)
pp. 1361-1371

This paper presents an efficient sequential circuit automatic test generation algorithm. The algorithm is based on PODEM and uses a nine-valued logic model. Among the novel features of the algorithm are use of Initial Timeframe Algorithm and correct implementation of a solution to the Previous State Information Problem. The Initial Timeframe Algorithm, one of the most important aspects of the test generator, determines the number of timeframes required to excite the fault for which a test is to be derived and the number of timeframes required to observe the excited fault. Correct determination of the number of timeframes in which the fault should be excited (activated) and observed saves the test generator from performing unnecessary search in the input space. Test generation is unidirectional, i.e., it is done strictly in forward time, and flip-flops in the initial timeframe are never assigned a state that needs to be justified later. The algorithm saves both the good and the faulty machine states after finding a test to aid in subsequent test generation. The Previous State Information Problem, which has often been ignored by existing test generators, is presented and discussed in the paper. Experimental results are presented to demonstrate the effectiveness of the algorithm.

[1] S. Seshu and D. N. Freeman, "The diagnosis of asynchronous sequential switching systems,"IRE Trans. Electron. Comput., vol. EC-11, no. 4, pp. 459-465, Aug. 1962.
[2] G. R. Putzolu and J. P. Roth, "A heuristic algorithm for the testing of asynchronous circuits,"IEEE Trans. Comput., vol. C-20, no. 6, pp. 639-647, June 1971.
[3] P. Muth, "A nine-valued circuit model for test generation,"IEEE Trans. Comput., vol. C-25, no. 6, pp. 630-636, June 1976.
[4] S. Mallela and S. Wu, "A sequential circuit test generation system,"Proc. Int. Test Conf., Nov. 1985, pp. 57-61.
[5] R. Marlett, "An effective test generation system for sequential circuits," inProc. Design Automat. Conf., June 1986, pp. 250-256.
[6] H-K. T. Ma, S. Devadas, A. R. Newton, and A. S-Vincentelli, "Test generation for sequential circuits,"IEEE Trans. Comput.-Aided Design ICS, pp. 1081-1093, Oct. 1988.
[7] V. D. Agrawal, K. T. Cheng, and P. Agrawal, "A directed search method for test generation using a concurrent fault simulator,"IEEE Trans. Comput.-Aided Design, vol. CAD-8, pp. 131-138, Feb. 1989.
[8] W. -T. Cheng and T. J. Chakraborty, "Gentest: An automatic testgeneration system for sequential circuits,"IEEE Comput., vol. 22, no. 4, pp. 43-49, Apr. 1989.
[9] A. Ghosh, S. Devadas, and A. R. Newton, "Test generation and verification for highly sequential circuits,"IEEE Trans. Comput.-Aided Design ICS, pp. 952-667, May 1991.
[10] E. Auth and M. H. Schulz, "Test-pattern generation algorithm for sequential circuits,"IEEE Des. Test Comput., vol. 3, pp. 72-86, June 1991.
[11] M.J. Bending, "HITEST--A knowledge-based test generation system,"IEEE Des. Test Comput., vol. 1, pp. 83-93, Feb. 1989.
[12] P. Goel, "An implicit enumeration algorithm to generate tests for combinational logic circuits,"IEEE Trans. Comput., vol. C-30, no. 3, pp. 215-222, March 1981.
[13] J. P. Roth, "Diagnosis of automata failures: A calculus and a method,"IBM J. Res. Develop., vol. 10, pp. 278-291, July 1966.
[14] W. Cheng and S. Davidson, "Sequential Circuit Test Generator (STG) Benchmark Results,"Proc. IEEE Int'l Symp. Circuits and Systems, IEEE Press, New York, 1989, pp. 1939-1941.
[15] N. Gouders and R. Kaibel, "Advanced techniques for sequential test generation,"Proc. 2nd Euro. Test Conf., 1991, pp. 293-300.
[16] L. Goldstein and E. Thigpen. "SCOAP: Sandia Controllability/Observability Analysis Program,"Proc. Design Automation Conf., 1980, pp. 190-196.
[17] T. P. Kelsey and K. K. Saluja, "Fast test generation for sequential circuits," inProc. Int. Conf. Comput. Aided Design, Nov. 1989, pp. 354-357.
[18] S. Patel and J. Patel, "Effectiveness of heuristics measure for automatic test generation,"Proc. 23rd Des. Automat. Conf., June 1986, pp. 547-552.
[19] F. Brglez and H. Fujiwara, "A neutral netlist of 10 combinational benchmark circuits and target translator in Fortran,"Proc. 1985 IEEE Int. Symp. Circuits Syst.(ISCAS), June 1985, pp. 663-698.

Index Terms:
sequential circuit test generation; automatic test generation algorithm; PODEM; nine-valued logic model; Initial Timeframe Algorithm; Previous State Information Problem; faulty machine states; automatic testing; logic testing; sequential circuits.
Citation:
T.P. Kelsey, K.K. Saluja, S.Y. Lee, "An Efficient Algorithm for Sequential Circuit Test Generation," IEEE Transactions on Computers, vol. 42, no. 11, pp. 1361-1371, Nov. 1993, doi:10.1109/12.247839
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