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Reconfiguring Processor Arrays Using Multiple-Track Models: The 3Track-Spare-Approach
November 1993 (vol. 42 no. 11)
pp. 1281-1293

[1] Y. Birk and J. B. Lotspiech, "On finding nonintersecting straight-line interconnections of grid points to the boundary," IBM, Almaden Research Center, San Jose, CA, Tech. Rep. RJ 7217 (67984), Dec. 1989.
[2] J. Bruck and V. Roychowdbury, "How to play bowling in parallel on the grid?"J. Algorithms, vol. 12, pp. 516-529, Sept. 1991.
[3] M. Chean and J. A. B. Fortes, "The full-use-of-suitable-spares (fuss) approach to hardware reconfiguration for fault-tolerant processor arrays,"IEEE Trans. Comput., vol. 39, pp. 564-571, Apr. 1990.
[4] J. S. N. Jean, H. C. Fu, and S. Y. Kung, "Yield enhancement for WSI array processors using two-and-half-track switches," inProc. Int. Conf. Wafer-Scale Integration, San Francsco, CA, Jan. 1990, pp. 243-250.
[5] L. Jervis, F. Lombardi, and D. Sciuto, "Orthogonal mapping: A reconfiguration strategy for fault tolerant VLSI/WSI 2-d arrays," inProc. Int. Workshop on Defect and Fault Tolerance in VLSI Systems, Oct. 1988.
[6] S. Khuller and J. Naor,Flow in Planar Graphs with Vertex Capacities. Preprint, Dept. of Comput. Sci., Stanford Univ., Stanford, CA.
[7] S.Y. Kung,VLSI Array Processors, Prentice Hall, Englewood Cliffs, N.J. 1988.
[8] S. Y. Kung, S. N. Jean, and C. W. Chang, "Fault-tolerant array processors using single-track switches,"IEEE Trans. Comput.vol. 38, pp. 501-514, Apr. 1989.
[9] F. Lombardi, M. G. Sami, and R. Stefanelli, "Reconfiguration of VLSI arrays by covering,"IEEE Trans. Comput.-Aided Design IC Syst., vol. 8, no. 9, pp. 952-965, Sept. 1989.
[10] R. Melhelm and J. Ramirez, "Reconfiguration of computational arrays with multiple redundancy,"Proc. Int. Conf. Parallel Processing, 1991.
[11] C. H. Papadimitriou and K. Steiglitz,Combinatorial Optimization: Algorithms and Complexity. Englewood Cliffs, NJ: Prentice-Hall, 1982.
[12] V. P. Roychowdbury, J. Bruck, and T. Kailith, "Efficient algorithms for reconfiguration in VLSI/WSI arrays,"IEEE Trans. Comput.(Special Issue on Fault-Tolerant Computing), vol. 39, pp. 480-489, Apr. 1990.
[13] T. Varvarigou, V. Roychowdhury, and T. Kailath, "New algorithms for reconfiguring VLSI/WSI arrays,"J. VLSI Signal Processing, vol. 3, no. 4, pp. 329-344, Oct. 1991.
[14] T. Varvarigou, V. P. Roychowdbury, and T. Kailith, "A polynomial time algorithm for reconfiguring multiple track models,"IEEE Trans. Comput., vol. 42, no. 4, pp. 385-395, Apr. 1993.
[15] Y. X. Wong, "Approximate estimation of reliability, mean-time-to-failure, and optimal redundancy of fault-tolerant processor arrays," Ph.D. dissertation, Purdue Univ., West Lafayette, IN, May 1990.
[16] H. Y. Youn and A. D. Singh, "Bounded channel width restructuring algorithm for VLSI/WSI arrays with channel faults," presented at HFTM, June 1989, Univ. of Illinois, Urbana, IL, June 1989.
[17] R. Miller, V. K. Prasanna Kumar, D. Reisis, and Q. F. Stout, "Meshes with reconfigurable buses," inProc. 5th MIT Conf. Advanced Res. VLSI(Cambridge, MA), 1988, pp. 163-178.

T.A. Varvarigou, V.P. Roychowdhury, T. Kailath, "Reconfiguring Processor Arrays Using Multiple-Track Models: The 3Track-Spare-Approach," IEEE Transactions on Computers, vol. 42, no. 11, pp. 1281-1293, Nov. 1993, doi:10.1109/12.247834
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