This Article 
 Bibliographic References 
 Add to: 
Testing of Fault-Tolerant Hardware Through Partial Control of Inputs
October 1993 (vol. 42 no. 10)
pp. 1267-1271

The problem of testing fault-tolerant redundant digital systems is investigated. To test redundant systems through normal voter outputs, independent control of the output of each replicated unit is required. In the past it was assumed that independent control of the output of a replicated unit requires independent control of all of its inputs. The authors show that partial control of inputs is actually required. The critical input set problem, which is the problem of finding a set of inputs that need to be independently controlled, is formulated. Solutions are offered for different testing strategies, including exhaustive testing and deterministic testing, and for different levels of circuit description.

[1] A. E. Barbour and A. S. Wojcik, "A general, constructive approach to fault-tolerant design using redundancy,"IEEE Trans. Comput., vol. C-38, pp. 15-29, 1989.
[2] M. Nicolaidis, "Self-exercising checkers for unified built-in self-test (UBIST),"IEEE Trans. Comput.-Aid. Des., vol. CAD-X, pp. 203-218, Mar. 1989.
[3] C. E. Stroud and A. E. Barbour, "Design for testability and test generation for static redundancy system level fault-tolerant circuits," inProc. IEEE Int. Test Conf., Washington DC, Aug. 29-31, 1989, pp. 812-818.
[4] R. Brayton, G. Hachtel, C. McMullen, and A. Sangio-Vincentelli,Logic Minimization Algorithms for VLSI Synthesis. Boston, MA: Kluwer Academic, 1984.
[5] F. Brlez and H. Fujiwara, "A neutral netlist of 10 combinational benchmark designs and a special translator in Fortran," presented at the Int. Symp. Circuits Syst., June 1985.
[6] J. von Neumann, "Probabilistic logic and the synthesis of reliable organisms from unreliable components," inAutomata Studies, Annals of Mathematical Studies. Princeton, NJ: Princeton University Press, 1956, pp. 43-98.
[7] Z. Kohavi,Switching and Finite Automata Theory. New York: McGraw-Hill, 1978.
[8] M. R. Garey and D. S. Johnson,Computers and Intractability: A Guide to Theory of NP-Completeness. San Francisco, CA: Freeman, 1979.
[9] I. Pomeranz and S.M. Reddy, "Compactest: A Method to Generate Compact Test Sets for Combinational Circuits,"Proc. Int'l Test Conf., IEEE CS Press, 1991, pp. 194-203.
[10] I. Pomeranz and S. M. Reddy, "Testing of fault-tolerant hardware through partial control of inputs," Tech. Rep. 25-11-119, Elec. Comput. Eng. Dep., Univ. Iowa.

Index Terms:
fault-tolerant hardware; redundant digital systems; critical input set problem; testing strategies; exhaustive testing; deterministic testing; circuit description; computer testing; fault tolerant computing.
I. Pomeranz, S.M. Reddy, "Testing of Fault-Tolerant Hardware Through Partial Control of Inputs," IEEE Transactions on Computers, vol. 42, no. 10, pp. 1267-1271, Oct. 1993, doi:10.1109/12.257713
Usage of this product signifies your acceptance of the Terms of Use.