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Issue No.10 - October (1993 vol.42)
pp: 1247-1252
ABSTRACT
<p>The Gamma interconnection network (GIN) is composed of 3*3 basic building blocks, with interconnecting patterns between stages following the plus-minus-2/sup i/ functions. The authors consider modifications to the GIN by altering the interconnecting patterns between stages so as to achieve high terminal reliability between any source-destination pair, resulting in the reliable GIN (REGIN). A type of REGIN's ensures totally disjoint paths in existence from any source to any destination, thereby capable of tolerating an arbitrary single fault. If several building blocks (i.e., 3*3 switches) are fabricated in one chip with very large scale integrated (VLSI) technology, the layout area and the pin count are less for the REGIN than for its GIN counterpart as a result of the change in the interconnecting patterns, giving rise to potential cost reduction. The terminal reliability of the REGIN is derived and compared with that of a compatible GIN. In addition, the performance of the REGIN is evaluated using simulation.</p>
INDEX TERMS
disjoint paths; Gamma interconnection networks; high terminal reliability; source-destination pair; VLSI; layout area; pin count; simulation; performance; fault tolerant computing; multiprocessor interconnection networks; network routing; performance evaluation.
CITATION
Po-Jen Chuang, Chwan-Hwa Wu, "Creating Disjoint Paths in Gamma Interconnection Networks", IEEE Transactions on Computers, vol.42, no. 10, pp. 1247-1252, October 1993, doi:10.1109/12.257710
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