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Parallel High-Radix Nonrestoring Division
October 1993 (vol. 42 no. 10)
pp. 1234-1246

An algorithm for high-radix nonrestoring division is proposed which combines a cost-efficient quotient estimation technique with collapsing of the division into one operation each iteration. The quotient estimation technique is a direct combinatorial algorithm which allows a more generalized partial remainder than similar studies. In addition, the successor partial remainder is calculated directly from the previous partial remainder. The intermediate steps of calculating the next quotient estimate, multiplying it by the divisor, and then subtracting the result from the previous remainder are telescoped into one step. This is possible due to the use of simple direct combinatorial equations for the quotient estimate. Thus, one operation is used to generate the next remainder from the previous remainder. This operation is similar to a multiplication with a reduced carry propagate adder. This algorithm reduces the latency of each iteration to less than the delay of one multiplication. Thus, high-radix nonrestoring division is possible with a low latency and no need for an off-chip ROM to hold a quotient estimate.

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Index Terms:
parallel high-radix nonrestoring division; quotient estimation; combinatorial algorithm; generalized partial remainder; carry propagate adder; latency; computer arithmetic; high-radix division; logic design; SRT division; digital arithmetic; logic design.
Citation:
E.M. Schwarz, M.J. Flynn, "Parallel High-Radix Nonrestoring Division," IEEE Transactions on Computers, vol. 42, no. 10, pp. 1234-1246, Oct. 1993, doi:10.1109/12.257709
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