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A Reduced-Area Scheme for Carry-Select Adders
October 1993 (vol. 42 no. 10)
pp. 1163-1170

The carry-select or conditional-sum adders require carry-chain evaluations for each block for both the values of block-carry-in, 0 and 1. The author introduces a scheme to generate carry bits with block-carry-in 1 from the carries of a block with block-carry-in 0. This scheme is then applied to carry-select and parallel-prefix adders to derive a more area-efficient implementation for both the cases. The proposed carry-select scheme is assessed relative to carry-ripple, classical carry-select, and carry-skip adders. The analytic evaluation is done with respect to the gate-count model for area and gate-delay units for time.

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Index Terms:
reduced-area; carry-select adders; conditional-sum adders; carry-chain evaluations; gate-count; gate-delay; analytic evaluation; carry-ripple; classical carry-select; carry-skip adders; parallel-prefix adders; area-efficient; adders; logic circuits; logic design.
Citation:
A. Tyagi, "A Reduced-Area Scheme for Carry-Select Adders," IEEE Transactions on Computers, vol. 42, no. 10, pp. 1163-1170, Oct. 1993, doi:10.1109/12.257703
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