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A. Tyagi, "A ReducedArea Scheme for CarrySelect Adders," IEEE Transactions on Computers, vol. 42, no. 10, pp. 11631170, October, 1993.  
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@article{ 10.1109/12.257703, author = {A. Tyagi}, title = {A ReducedArea Scheme for CarrySelect Adders}, journal ={IEEE Transactions on Computers}, volume = {42}, number = {10}, issn = {00189340}, year = {1993}, pages = {11631170}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.257703}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  A ReducedArea Scheme for CarrySelect Adders IS  10 SN  00189340 SP1163 EP1170 EPD  11631170 A1  A. Tyagi, PY  1993 KW  reducedarea; carryselect adders; conditionalsum adders; carrychain evaluations; gatecount; gatedelay; analytic evaluation; carryripple; classical carryselect; carryskip adders; parallelprefix adders; areaefficient; adders; logic circuits; logic design. VL  42 JA  IEEE Transactions on Computers ER   
The carryselect or conditionalsum adders require carrychain evaluations for each block for both the values of blockcarryin, 0 and 1. The author introduces a scheme to generate carry bits with blockcarryin 1 from the carries of a block with blockcarryin 0. This scheme is then applied to carryselect and parallelprefix adders to derive a more areaefficient implementation for both the cases. The proposed carryselect scheme is assessed relative to carryripple, classical carryselect, and carryskip adders. The analytic evaluation is done with respect to the gatecount model for area and gatedelay units for time.
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