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IEEE Transactions on Computers
October 1993 (vol. 42 no. 10)
ISSN: 0018-9340
Table of Contents
Editorial
Editorial
(Abstract)
E.E. Swartzlanger, Jr.
pp. 1153
ABSTRACT
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PAPERS
A Quantitative Evaluation of Cache Types for High-Performance Computer Systems
(Abstract)
C.E. Wu
Y. Hsu
Y.-H. Liu
pp. 1154-1162
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A Reduced-Area Scheme for Carry-Select Adders
(Abstract)
A. Tyagi
pp. 1163-1170
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A Parallel Computational Model for Integrated Speech and Natural Language Understanding
(Abstract)
Sang-Hwa Chung
D.I. Moldovan
R.F. DeMara
pp. 1171-1183
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The Completion Time of Programs on Processors Subject to Failure and Repair
(Abstract)
P.F. Chimento
K.S. Trivedi
pp. 1184-1194
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Fault-Tolerant Design Strategies for High Reliability and Safety
(Abstract)
N.F. Vaidya
D.K. Pradhan
pp. 1195-1206
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Assessing Reliability of Multistage Interconnection Networks
(Abstract)
C.J. Colbourn
J.S. Devitt
D.D. Harms
M. Kraetzl
pp. 1207-1221
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Approximation, Dimension Reduction, and Nonconvex Optimization Using Linear Superpositions of Gaussians
(Abstract)
A. Saha
Chuan-Lin Wu
Dun-Sung Tang
pp. 1222-1233
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Parallel High-Radix Nonrestoring Division
(Abstract)
E.M. Schwarz
M.J. Flynn
pp. 1234-1246
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CORRESPONDENCE
Creating Disjoint Paths in Gamma Interconnection Networks
(Abstract)
Nian-Feng Tzeng
Po-Jen Chuang
Chwan-Hwa Wu
pp. 1247-1252
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Bounds on the Performance of Message Routing Heuristics
(Abstract)
P.J. Bernhard
pp. 1253-1256
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Borrow: A Fault-Tolerance Scheme for Wavefront Array Processors
(Abstract)
T. Stouraitis
pp. 1257-1261
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Design of Efficient Error-Correcting Balanced Codes
(Abstract)
S. Al-Bassam
B. Bose
pp. 1261-1266
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Testing of Fault-Tolerant Hardware Through Partial Control of Inputs
(Abstract)
I. Pomeranz
S.M. Reddy
pp. 1267-1271
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A Boolean Neural Network Approach for the Traveling Salesman Problem
(Abstract)
S. Bhide
N. John
M.R. Kabuka
pp. 1271-1278
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A Modified Massey-Omura Parallel Multiplier for a Class of Finite Fields
(Abstract)
M.A. Hasan
M.Z. Wang
V.K. Bhargava
pp. 1278-1280
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