Issue No.09 - September (1993 vol.42)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.241604
<p>The authors propose design techniques that may significantly simplify the cache access path, and hence offer the opportunity of shorter cycle time or fewer pipeline stages. Their proposals are based on highly accurate prediction methods that allow them to efficiently resolve address translation information early in the pipe.</p>
high-performance processors; real address prediction; cache access path; shorter cycle time; pipeline stages; prediction methods; address translation; buffer storage; pipeline processing.
K.A. Hua, L.A. Liu, J. Peir, "Designing High-Performance Processors Using Real Address Prediction", IEEE Transactions on Computers, vol.42, no. 9, pp. 1146-1151, September 1993, doi:10.1109/12.241604