This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Designing High-Performance Processors Using Real Address Prediction
September 1993 (vol. 42 no. 9)
pp. 1146-1151

The authors propose design techniques that may significantly simplify the cache access path, and hence offer the opportunity of shorter cycle time or fewer pipeline stages. Their proposals are based on highly accurate prediction methods that allow them to efficiently resolve address translation information early in the pipe.

[1] J.L. Hennessy and David A. Patterson,Computer Architecture: A Quantitative Approach, Morgan Kaufmann, San Mateo, Calif., 1990.
[2] C. J. Conti, "Concepts for buffer storage,"IEEE Comput. Group News, vol. 2, pp. 9-13, Mar. 1969.
[3] A. Smith, "Cache Memories,"Computing Surveys, Vol. 14, No. 3, Sept. 1982, pp. 473- 530.
[4] P. J. Denning, "Virtual memory,"ACM Comput. Surveys, vol. 2, pp. 153-189, 1970.
[5] IBM Corp.,IBM System/370 Extended Architecture: Principles of Operation, publ. SA22-7085.
[6] K. Hua, A. Hunt, L. Liu, J. Peir, D. Pruett, and J. Temple, "Early resolution of address translation in cache design," inProc. 1990 IEEE Int. Conf. Comput. Des., Sept. 1990.
[7] S. G. Tucker, "The IBM 3090 systems: An overview,"IBM Syst. J., vol. 25, no. 6, Jan. 1986.
[8] J.R. Goodman, "Coherency for Multiprocessor Virtual Address Caches,"Proc. ASPLOS, Second Int'l Conf. Architectural Support for Programming Languages and Operating Systems, Oct. 1987, pp. 72-81.
[9] M. Morioka, K. Kurita, H. Kobayashi, and H. Sawamoto, "Cache design for high performance computers with BiCMos VLSIs," inProc. 1990 Int. Conf. Comput. Des., Oct. 1990, pp. 413-416.
[10] D.A. Wood et al., "An In-Cache Address Translation Mechanism,"Proc. 13th Ann. Int'l Symp. Computer Architecture, No. 719, Computer Society Press, Los Alamitos, Calif., 1986, pp. 358-365.
[11] R. Groves and R. Oehler, "RISC system/6000 processor architecture," inIBM RISC System/6000 Technology, IBM Corporation, 1990, publ. SA23-2619.
[12] Digital Equipment Corporation,VAX Architecture Handbook, 1981.
[13] J. Pomerene, T. Puzak, R. Rechtschaffen, H. Schorr, and I. Wladawsky-Berger, "Mechanism for acceleration of cache references,"IBM Tech. Disclos. Bull., vol. 25(3B), pp. 1740-1744, Aug. 1982.
[14] J.H. Chang, H. Chao, and K. So, "Cache Design of a Sub-Micron CMOS System/370,"Proc. 14th Ann. Int'l Symp. Computer Architecture, No. 776, Computer Society Press, Los Alamitos, Calif., 1987, pp. 208-213.
[15] K. So and R. Techtschaffen, "Cache operations by MRU change," inProc. IEEE Int. Conf. Comput. Des., Oct. 1990.

Index Terms:
high-performance processors; real address prediction; cache access path; shorter cycle time; pipeline stages; prediction methods; address translation; buffer storage; pipeline processing.
Citation:
K.A. Hua, L.A. Liu, J. Peir, "Designing High-Performance Processors Using Real Address Prediction," IEEE Transactions on Computers, vol. 42, no. 9, pp. 1146-1151, Sept. 1993, doi:10.1109/12.241604
Usage of this product signifies your acceptance of the Terms of Use.