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A Systolic Architecture for Computing Inverses and Divisions in Finite Fields GF(2/sup m/)
September 1993 (vol. 42 no. 9)
pp. 1141-1146

A new serial-in serial-out systolic array is presented for performing the element inversion in GF(2/sup m/) with the standard basis representation. The architecture is highly regular, modular, nearest neighbor connected, and thus well suited to VLSI implementation, It has a latency of 7m-3 clock cycles and a throughput rate of one result per 2m)-1 clock cycles. This speed performance is much better than those of the previous implementations. Without change in hardware design, the proposed inversion array can be directly used for computing the division in GF(2/sup m/).

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Index Terms:
systolic architecture; inverses; divisions; finite fields; VLSI implementation; speed performance; inverse problems; systolic arrays; VLSI.
Citation:
Chin-Liang Wang, Jung-Lung Lin, "A Systolic Architecture for Computing Inverses and Divisions in Finite Fields GF(2/sup m/)," IEEE Transactions on Computers, vol. 42, no. 9, pp. 1141-1146, Sept. 1993, doi:10.1109/12.241603
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