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Yield Analysis of Reconfigurable Array Processors Based on Multiple-Level Redundancy
September 1993 (vol. 42 no. 9)
pp. 1136-1141

Presents and analyzes a new multiple-level redundancy scheme based on hierarchical and element level redundancy for the enhancement of yield and reliability of large area array processors. This scheme can effectively tolerate not only the random defects/faults, but also the clustered defects/faults. The analysis presented here is general in that it takes into account the chip-kill defects occurring in the support circuit area of the array processors and is applicable to a variety of array processors. The authors derive bounds for the support circuit area which will be useful in selecting the most cost-effective redundancy scheme for a given application. The concept of subprocessing element-level redundancy is discussed and it is shown that a combination of subprocessing element-level redundancy with hierarchical redundancy offers significant yield improvements, especially for array processors with large area processing elements. The problem of optimal redundancy is also addressed.

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Index Terms:
reconfigurable array processors; multiple-level redundancy; redundancy; yield; reliability; chip-kill defects; optimal redundancy; array processors; hierarchical redundancy; fault tolerant computing; fault tolerant computing; parallel processing; reconfigurable architectures; redundancy.
Citation:
Y.-Y. Chen, S.J. Upadhyaya, "Yield Analysis of Reconfigurable Array Processors Based on Multiple-Level Redundancy," IEEE Transactions on Computers, vol. 42, no. 9, pp. 1136-1141, Sept. 1993, doi:10.1109/12.241602
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