Issue No.09 - September (1993 vol.42)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.241598
<p>This paper presents several techniques for tolerating faults in d-dimensional mesh and hypercube architectures. The approach consists of adding spare processors and communication links so that the resulting architecture will contain a fault-free mesh or hypercube in the presence of faults. The authors optimize the cost of the fault-tolerant architecture by adding exactly k spare processors (while tolerating up to k processor and/or link faults) and minimizing the maximum number of links per processor. For example, when the desired architecture is a d-dimensional mesh and k=1, they present a fault-tolerant architecture that has the same maximum degree as the desired architecture (namely, 2d) and has only one spare processor. They also present efficient layouts for fault-tolerant two- and three-dimensional meshes, and show how multiplexers and buses can be used to reduce the degree of fault-tolerant architectures. Finally, they give constructions for fault-tolerant tori, eight-connected meshes, and hexagonal meshes.</p>
fault-tolerant meshes; hypercubes; d-dimensional mesh; fault-tolerant architecture; multiplexers; buses; tori; hexagonal meshes; fault tolerant computing; hypercube networks; performance evaluation.
R. Cypher, C. Ho, "Fault-Tolerant Meshes and Hypercubes with Minimal Numbers of Spares", IEEE Transactions on Computers, vol.42, no. 9, pp. 1089-1104, September 1993, doi:10.1109/12.241598