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Classification of Faults in Synchronous Sequential Circuits
September 1993 (vol. 42 no. 9)
pp. 1066-1077

Undetectable and redundant faults in synchronous sequential circuits are analyzed. A distinction is drawn between undetectable faults and faults that are never manifested as output errors. The latter are classified as redundant. It is shown that there are faults for which a test sequence does not exist; however, under certain initial conditions (or initial states) of the circuit, faulty behavior may be observed. Such faults are called partially detectable faults. A partially detectable fault is undetectable, but is not redundant, as it affects circuit operation under some conditions. The author observes that the notion of redundancy cannot be separated from the mode of operation of the circuit. Two modes of operation are considered, representative of common modes, called the synchronization mode and the free mode. Accordingly, the identification of redundant faults calls for different test generation strategies. Two test strategies to generate tests for detectable faults and partial tests for partially detectable faults are defined, called the restricted test strategy and the unrestricted test strategy.

[1] M. Abramovici and M. A. Breuer, "On redundancy and fault detection in sequential circuits,"IEEE Trans. Comput., pp. 864-865, Nov. 1979.
[2] M. Abramovici, M. A. Breuer, and A. D. Friedman,Digital Systems Testing and Testable Design. Computer Science Press, 1990.
[3] H. Fujiwara,Logic Testing and Design for Testability. Cambridge, MA: MIT Press, 1985.
[4] F. Hennie,Finite-State Models for Logical Machines. New York: Wiley, 1968.
[5] A. D. Friedman and P. R. Menon,Fault Detection in Digital Circuits. Englewood Cliffs, NJ: Prentice-Hall, 1971.
[6] H. Kubo, "A procedure for generating test sequences to detect sequential circuit failures,"NEC Res. Develop., no. 12, Oct. 1968.
[7] J. J. Thomas, "Automated diagnostic test programs for digital networks,"Computer Design, pp. 63-67, Aug. 1971.
[8] P. Muth, "A nine valued circuit model for test generation,"IEEE Trans. Comput., pp. 630-636, June 1976.
[9] M. A. Breuer and A. D. Friedman,Diagnosis and Reliable Design of Digital Systems. Computer Science Press, 1976.
[10] R. Marlett, "EBT: A comprehensive test generation system for highly sequential circuits," inProc. 15th Design Automat. Conf., June 1978, pp. 335-339.
[11] S. Seshu, "On an improved diagnosis program,"IEEE Trans. Comput., pp. 76-79, Feb. 1965.
[12] T. J. Snethen, "Simulator-oriented fault test generator," inProc. Design Auto. Conf., 1977, pp. 88-93.
[13] S. Shteingart, A. W. Nagle, and J. Grason, "RTG: Automatic register level test generator," inProc. 22nd Design Automat. Conf., June 1985, pp. 803-807.
[14] S. Mallela and S. Wu, "A sequential test generation system," inProc. Int. Test Conf., Sept. 1985, pp. 57-61.
[15] R. Marlett, "An effective test generation system for sequential circuits," inProc. Design Automat. Conf., June 1986, pp. 250-256.
[16] T. P. Kelsey and K. K. Saluja, "Fast test generation for sequential circuits," inProc. Int. Conf. Comput. Aided Design, Nov. 1989, pp. 354-357.
[17] W-T. Cheng, "The back algorithm for sequential test generation," inProc. Int. Conf. Comput. Design, Oct. 1988, pp. 66-69.
[18] W-T. Cheng and T. J. Chakraborty, "Gentest: An automatic test generation system for sequential circuits,"Computer, pp. 43-49, Apr. 1989.
[19] T. Ogihara, S. Saruyama, and S. Murai, "Test generation for seauential circuits using individual initial value propagation," inProc. Int. Conf. Comput. Aided Design, Nov. 1988, pp. 424-427.
[20] V. D. Agrawal, K. T. Cheng, and P. Agrawal, "CONTEST: A concurrent test generator for sequential circuits" inProc. Design Automat. Conf., June 1988, pp. 84-89.
[21] H-K. T. Ma, S. Devadas, A. R. Newton, and A. S-Vincentelli, "Test generation for sequential circuits,"IEEE Trans. Comput.-Aided Design ICS, pp. 1081-1093, Oct. 1988.
[22] K-T. Cheng and J. Y. Jou, "Functional test generation for finite state machines," inProc. Int. Test Conf., 1990, pp. 162-168.
[23] R. V. Hudly and S. C. Seth, "Testability analysis of synchronous sequential circuits based on structural data," inProc. Int. Test Conf., 1989, pp. 364-372.
[24] S. M. Thatte and J. A. Abraham, "Test generation for microprocessors,"IEEE Trans. Comput., pp. 429-441, June 1980.
[25] K. Sabnani and A. Dahbura, "A protocol test generation procedure,"Comput. Networks ISDN Syst., North-Holland, no. 15, pp. 285-297, 1988.
[26] A. T. Dahbura, M. U. Uyar, and C. W. Yau, "An optimal test sequence for the JTAG/IEEE P1149.1 test access port controller," inProc. Int. Test Conf., 1989, pp. 55-62.
[27] M. S. Abadir and H. K. Reghabati, "Functional test generation for digital circuits described using binary decision diagram,"IEEE Trans. Comput., vol. C-35, no. 4, pp. 375-379, Apr. 1986.
[28] W.R. Stevens,Advanced Programming in the Unix Environment, Addison Wesley, New York, 1992.
[29] V. D. Agrawal, K. T. Cheng, and P. Agrawal, "A directed search method for test generation using a concurrent fault simulator,"IEEE Trans. Comput.-Aided Design, vol. CAD-8, pp. 131-138, Feb. 1989.
[30] S. Devadas, H.K. Ma, and A.R. Newton, "Redundancies and Don't Cares in Sequential Logic Synthesis,"J. Electronic Testing: Theory and Applications, Jan. 1990, pp. 15-30.
[31] E. B. Eichelberger and T. W. Williams, "A logic design structure for LSI testing," inProc. 14th Design Automat. Conf., 1977, pp. 462-468.
[32] K. T. Cheng, "On removing redundancy in sequential circuits," inProc. 28th Design Auto. Conf., June 1991, pp. 164-169.
[33] I. Pomeranz and S. M. Reddy, "Test generation for synchronous sequential circuits based on fault extraction," inProc. 1991 Int. Conf. CAD, Nov. 1991, pp. 450-453.
[34] I. Pomeranz and S. M. Reddy, "Test generation for synchronous sequential circuits using multiple observation times," inProc. Fault-Tolerant Comput. Symp., 1991, pp. 52-59.
[35] Z. Kohavi,Switching and Finite Automata Theory. New York: McGraw-Hill, 1978.
[36] A. D. Friedman, "Fault detection in redundant circuits,"IEEE Trans. Comput., pp. 66-73, Feb. 1966.
[37] I. Pomeranz and S. M. Reddy, "The multiple observation time test strategy,"IEEE Trans. Comput., (Special Issue on Fault-Tolerant Computing), pp. 627-637, May 1992.

Index Terms:
redundant faults; undetectable faults; test sequence; initial conditions; partially detectable faults; synchronization mode; free mode; synchronous sequential circuits; faults classification; combinatorial circuits; fault location; logic testing; sequential circuits; synchronisation.
I. Pomeranz, S.M. Reddy, "Classification of Faults in Synchronous Sequential Circuits," IEEE Transactions on Computers, vol. 42, no. 9, pp. 1066-1077, Sept. 1993, doi:10.1109/12.241596
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