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Issue No.09 - September (1993 vol.42)
pp: 1035-1044
ABSTRACT
<p>A new design approach, based on multiple signature analysis, for self-diagnostic boards is presented. For this approach, test responses from all chips on the board are compressed into space-time signatures using nonbinary multiple error-correcting codes, and faulty chips are identified by analyzing relations between distortions in these signatures. This approach results in a considerable reduction of a hardware overhead, required for diagnostics, as compared with the straightforward approach where separate signatures are computed for each chip on the board. The diagnostic approach presented can also be used for identification of faulty boards in a system or for faulty processors in a multiprocessor environment.</p>
INDEX TERMS
self-diagnostic boards; multiple signature analysis; test responses; multiple error-correcting codes; faulty chips; faulty boards; multiprocessor environment; diagnostics; error correction codes; logic testing; Reed-Solomon codes.
CITATION
M.G. Karpovsky, S.M. Chaudhry, "Design of Self-Diagnostic Boards by Multiple Signature Analysis", IEEE Transactions on Computers, vol.42, no. 9, pp. 1035-1044, September 1993, doi:10.1109/12.241593
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