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P.D. Fisher, ShengFu Wu, "RaceFree State Assignments for Synthesizing LargeScale Asynchronous Sequential Logic Circuits," IEEE Transactions on Computers, vol. 42, no. 9, pp. 10251034, September, 1993.  
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@article{ 10.1109/12.241592, author = {P.D. Fisher and ShengFu Wu}, title = {RaceFree State Assignments for Synthesizing LargeScale Asynchronous Sequential Logic Circuits}, journal ={IEEE Transactions on Computers}, volume = {42}, number = {9}, issn = {00189340}, year = {1993}, pages = {10251034}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.241592}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  RaceFree State Assignments for Synthesizing LargeScale Asynchronous Sequential Logic Circuits IS  9 SN  00189340 SP1025 EP1034 EPD  10251034 A1  P.D. Fisher, A1  ShengFu Wu, PY  1993 KW  state assignments; largescale; asynchronous sequential logic circuits; racefree; race condition; intrinsic race; generated race; NodeWeight Diagram; cycles; states; asynchronous sequential logic; hazards and race conditions; logic design; sequential circuits; state assignment. VL  42 JA  IEEE Transactions on Computers ER   
A state assignment technique is introduced for synthesizing largescale asynchronous sequential logic circuits (ASLCs). It provides a systematic and efficient approach for generating racefree state assignments. A race condition is classified as being either an intrinsic race (IR) or or a generated race. Intrinsic races decompose into two subclassifications: visible intrinsic races and hidden intrinsic races. Algorithms have been developed to identify and eliminate these races. A graph, referred to as a NodeWeight Diagram, facilitates the process of making state assignments and guarantees that no races are generated. Moreover, it provides a convenient and efficient method for investigating the implications of selecting from an allowed set of alternative racefree state assignments. The state assignment technique described adds cycles and states, as needed, to avoid IRs and always attempts to use the minimum or nearminimum number of state variables and states. This technique has been implemented and incorporated into an ASLC design automation system. Experimental results show that it provides significantly better results than other approaches in terms of the computation time required to make the assignments and the number of state variables required to achieve racefree ASLCs.
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