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Issue No.08 - August (1993 vol.42)
pp: 968-980
ABSTRACT
<p>Reed-Muller coefficients are used to generate a test-pattern selection procedure for detecting single stuck-at faults. This procedure is based on the heuristics deduced from the way in which the spectral coefficients are affected by such faults. The changes that the spectral coefficients undergo are also compared with the fault models used most frequently to model defects in combinational circuits. The proposed pattern-generating procedure does not need a simulation of the circuit for each of the possible stuck-at faults, and its complexity is proportional to the number of gates in the circuit. The proportionality constant increases exponentially as the number of inputs in the circuit increases. To evaluate the performance of the proposed method, its application to some benchmark circuits, including the ALU 74181, is presented.</p>
INDEX TERMS
test pattern generation; Reed-Muller coefficients; test-pattern selection procedure; single stuck-at faults; heuristics; spectral coefficients; combinational circuits; pattern-generating procedure; complexity; benchmark circuits; ALU 74181; computational complexity; logic testing.
CITATION
J. Ortega, A.L. Ruiz, A. Prieto, F.J. Pelayo, "Test-Pattern Generation Based on Reed-Muller Coefficients", IEEE Transactions on Computers, vol.42, no. 8, pp. 968-980, August 1993, doi:10.1109/12.238487
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