|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
 Digg  Furl  Spurl  Blink  Simpy  Google  Del.icio.us  Y!MyWeb | ||
| Search | ||
| ||
| ASCII Text | x | ||
| G. Alia, E. Martinelli, "On the Lower Bound to the VLSI Complexity of Number Conversion from Weighted to Residue Representation," IEEE Transactions on Computers, vol. 42, no. 8, pp. 962-967, August, 1993. | |||
| BibTex | x | ||
| @article{ 10.1109/12.238486, author = {G. Alia and E. Martinelli}, title = {On the Lower Bound to the VLSI Complexity of Number Conversion from Weighted to Residue Representation}, journal ={IEEE Transactions on Computers}, volume = {42}, number = {8}, issn = {0018-9340}, year = {1993}, pages = {962-967}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.238486}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - On the Lower Bound to the VLSI Complexity of Number Conversion from Weighted to Residue Representation IS - 8 SN - 0018-9340 SP962 EP967 EPD - 962-967 A1 - G. Alia, A1 - E. Martinelli, PY - 1993 KW - weighted representation; lower bound; VLSI complexity; number conversion; residue representation; pipeline scheme; optimal structure; single CMOS custom chip; CMOS integrated circuits; computational complexity; digital arithmetic; VLSI. VL - 42 JA - IEEE Transactions on Computers ER - | |||
A lower bound AT/sup 2/= Omega (n/sup 2/) for the conversion from positional to residue representation is derived according to VLSI complexity theory, and existing solutions for the same problem are briefly reviewed in the light of such a bound. A VLSI system is proposed, one that operates according to a pipeline scheme and works asymptotically emulating an optimal structure, independently of residue number system parameters. This solution has been applied to a design of specific size (64-b input stream), and it has been found that a single CMOS custom chip can implement the design with a throughput of one residue representation every 30-40 ns.
[1] R. M. Capocelli and R. Giancarlo, "Efficient VLSI networks for converting an integer from binary to residue numbers and vice versa,"IEEE Trans. Circuits Syst., vol. CAS-35, no. 11, pp. 1425-1430, 1988.
[2] G. Alia and E. Martinelli, "A VLSI structure forx(modm) operation,"J. VLSI Signal Processing, vol. 1, pp. 257-264, 1990.
[3] G. Alia and E. Martinelli, "VLSI binary-residue converters for pipelined processing,"Comput. J., vol. 33, no. 5, pp. 473-475, 1990.
[4] C. D. Thompson, "A complexity theory for VLSI," Ph.D. dissertation, Dep. Comput. Sci., Carnegie Mellon Univ., 1980.
[5] N. S. Szabo and R. J. Tanaka,Residue Arithmetic and its Applications to Computer Technology. New York: McGraw-Hill, 1967.
[6] G. H. Hardy and E. M. Wright,An Introduction to the Theory of Numbers, 4th ed. London: Oxford, 1975.
[7] G. Bilardi and F. P. Preparata, "Area-time lower bound techniques with applications to sorting,"Algorithmica, vol. 1, no. 1, pp. 65-91, 1986.
[8] K. Mehlhorn, "AT2-optimal VLSI integer division and integer square rooting,"Integration, vol. 2, pp. 163-167, 1984.
[9] K. Melhorn and F. P. Preparata, "Area-time optimal VLSI integer multiplier with minimum computation time,"Inform. Contr., vol. 58, pp. 137-156, 1983.
[10] G. Alia and E. Martinelli, "A VLSI modulemmultiplier,"IEEE Trans. Comput., vol. C-40, no. 7, pp. 873-878, 1991.
[11] R. P. Brent and H. T. Kung, "A regular layout for parallel adders,"IEEE Trans. Comput., vol. C-31, no. 3, pp. 260-264, 1982.