Subscribe

Issue No.08 - August (1993 vol.42)

pp: 898-912

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.238481

ABSTRACT

<p>The use of generalized Hopfield neural networks in designing the checking circuitry of a concurrent testable circuit is discussed. The aliasing probability, a measure for evaluating the performance of the checking circuitry, is provided. It is shown how, by using spectral techniques based on the Reed-Muller transform, the aliasing probability can be expressed as a function of the Reed-Muller coefficients. Therefore, obtaining the checking circuitry means selecting a set of Reed-Muller spectral coefficients, with fewer elements than a given bound, that minimizes the aliasing probability. To apply the neural networks to design the checking circuitry for concurrent testing, the aliasing probability has been used as an energy function, and the Hopfield neural network has been modified to have an associated energy function with any type of polynomial dependence on the processor states.</p>

INDEX TERMS

generalised Hopfield neural network; performance evaluation; concurrent testing; checking circuitry; concurrent testable circuit; aliasing probability; spectral techniques; Reed-Muller transform; energy function; associated energy function; polynomial dependence; combinatorial circuits; fault tolerant computing; Hopfield neural nets; logic testing.

CITATION

J. Ortega, A. Prieto, A. Lloris, F.J. Pelayo, "Generalized Hopfield Neural Network for Concurrent Testing",

*IEEE Transactions on Computers*, vol.42, no. 8, pp. 898-912, August 1993, doi:10.1109/12.238481