This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Reconfigurability and Reliability of Systolic/Wavefront Arrays
July 1993 (vol. 42 no. 7)
pp. 854-862

The authors study fault-tolerant redundant structures for maintaining reliable arrays. In particular, they assume that the desired array (application graph) is embedded in a certain class of regular, bounded-degree graphs called dynamic graphs. The degree of reconfigurability (DR) and DR with distance (DR/sup d/) of a redundant graph are defined. When DR and DR/sup d/ are independent of the size of the application graph, the graph is finitely reconfigurable (FR) and locally reconfigurable (LR), respectively. It is shown that DR provides a natural lower bound on the time complexity of any distributed reconfiguration algorithm and that there is no difference between being FR and LR on dynamic graphs. It is also shown that if both local reconfigurability and a fixed level of reliability are to be maintained, a dynamic graph must be of a dimension at least one greater than the application graph. Thus, for example, a one-dimensional systolic array cannot be embedded in a one-dimensional dynamic graph without sacrificing either reliability or locality of reconfiguration.

[1] F. R. K. Chung, F. T. Leighton, and A. L. Rosenberg, "Diogenes: A methodology for designing fault-tolerant VLSI processing arrays," inProc. IEEE Int. Symp. Fault-Tolerant Computing, Milano, June 1983, pp. 26-32.
[2] P. R. Cappello and K. Steiglitz, "Digital signal processing applications of systolic algorithms," inCMU Conf. VLSI Systems and Computations, H. T. Kung, B. Sproull, and G. Steele, eds. Rockville, MD: Computer Science Press, Oct. 1981, pp. 19-21.
[3] J. W. Greene and A. El Gamal, "Configuration of VLSI arrays in the presence of defects,"J. ACM, vol. 31, no. 4, pp. 694-717, 1984.
[4] J. P. Hayes, "A graph model for fault-tolerant computing systems,"IEEE Trans. Comput., vol. C-25, no. 9, pp. 875-884, Sept. 1976.
[5] M. J. Iacoponi and S. F. McDonald, "Distributed reconfiguration and recovery in the advanced architecture on-board processor," inProc. IEEE Int. Symp. Fault-Tolerant Computing, Montreal, June 1991, pp. 436-443.
[6] K. Iwano and K. Steiglitz, "Testing for cycles in infinite graphs with periodic structure," inProc. 19th Annual ACM Symp. Theory Computing, New York, May 1987, pp. 46-55.
[7] K. Iwano and K. Steiglitz, "Planarity testing of doubly periodic infinite graphs,"Networks, vol. 18, no. 3, pp. 205-222, Fall 1988.
[8] K. Iwano and K. Steiglitz, "A semiring on convex polygons and zero-sum cycle problems,"SIAM J. Computing, vol. 19, no. 5, pp. 883-901, Oct. 1990.
[9] H. T. Kung, "Why systolic architectures?"IEEE Comput., vol. 15, no. 1, pp. 37-46, Jan. 1982.
[10] H. T. Kung and M. S. Lam, "Fault tolerant VLSI systolic arrays and two-level pipelines,"J. Parall. Distr. Proc., vol. 8, pp. 32-63, 1984.
[11] S.Y. Kung,VLSI Array Processors, Prentice Hall, Englewood Cliffs, N.J. 1988.
[12] S. Y. Kung, K. S. Arun, R. J. Gal-Ezer, and D. V. Bhaskar Rao, "Wavefront army processor: Languages, architecture, and applications,"IEEE Trans. Comput., vol. C-31, pp. 1054-1066, Nov. 1982.
[13] S. Y. Kung, S. N. Jean, and C. W. Chang, "Fault-tolerant array processors using single track switches,"IEEE Trans. Comput., vol. C-38, no. 4, pp. 501-514, Apr. 1989.
[14] S. D. Kugelmass and K. Steiglitz, "A scalable architecture for lattice-gas simulation,"J. Computational Physics, vol. 84, pp. 311-325, Oct. 1989.
[15] T. Leighton and C. E. Leiserson, "Wafer-scale integration of systolic arrays,"IEEE Trans. Comput., vol. C-34, no. 5, pp. 448-461, 1985.
[16] J. Orlin, "Some problems on dynamic/periodic graphs,"Progress in Combinatorial Optimization, W. R. Pulleyblank, ed. Orlando, FL: Academic Press, 1984, pp. 273-293.
[17] V. P. Roychowdhury, J. Bruck, and T. Kailath, "Efficient algorithms for reconfiguration in VLSI/WSI arrays,"IEEE Trans. Comput., vol. C-39, no. 4, pp. 480-489, Apr. 1990.
[18] M. Sami and R. Stefenelli, "Reconfiguration architecture for VLSI processing arrays," inProc. IEEE Int. Symp. Fault-Tolerant Computing, 1986, pp. 712-722.
[19] E. H.-M. Sha and K. Steiglitz, "Explicit constructions for reliable reconfigurable array architectures," inProc. 3rd IEEE Symp. Parallel Distributed Process., Dallas, TX, Dec. 1991, pp. 640-647.

Index Terms:
systolic arrays; wavefront arrays; reconfigurability; reliability; fault-tolerant redundant structures; reliable arrays; application graph; bounded-degree graphs; dynamic graphs; finitely reconfigurable; locally reconfigurable; lower bound; time complexity; fault tolerant computing; reconfigurable architectures; systolic arrays.
Citation:
E.H.-M. Sha, K. Steiglitz, "Reconfigurability and Reliability of Systolic/Wavefront Arrays," IEEE Transactions on Computers, vol. 42, no. 7, pp. 854-862, July 1993, doi:10.1109/12.237725
Usage of this product signifies your acceptance of the Terms of Use.