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Interlock Collapsing ALU's
July 1993 (vol. 42 no. 7)
pp. 825-839

A device capable of executing interlocked fixed point arithmetic logic unit (ALU) instructions in parallel with other instructions causing the execution interlock is presented. The device incorporates the design of a 3-1 ALU and can execute two's complement, unsigned binary, and binary logical operations. It is shown that status for ALU operations using a 3-1 ALU can be determined in a parallel fashion, resulting in the compliance of the proposed device with predetermined architectural behavior of single instruction execution. The device requires no more logic stages than does a 3-1 binary adder using a carry-save adder (CSA) followed by a carry-lookahead adder (CLA) design. Design considerations using a commonly available CMOS technology are also reported, indicating that the device will not increase the machine cycle of an implementation. It is suggested that the device can maintain full architectural compatibility.

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Index Terms:
interlocked fixed point arithmetic logic unit; two's complement; unsigned binary; binary logical operations; single instruction execution; carry-save adder; carry-lookahead adder; CMOS technology; machine cycle; architectural compatibility; adders; CMOS integrated circuits; digital arithmetic; parallel processing.
Citation:
S. Vassiliadis, J. Phillips, B. Blaner, "Interlock Collapsing ALU's," IEEE Transactions on Computers, vol. 42, no. 7, pp. 825-839, July 1993, doi:10.1109/12.237723
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