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K. Kota, J.R. Cavallaro, "Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for SpecialPurpose Processors," IEEE Transactions on Computers, vol. 42, no. 7, pp. 769779, July, 1993.  
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@article{ 10.1109/12.237718, author = {K. Kota and J.R. Cavallaro}, title = {Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for SpecialPurpose Processors}, journal ={IEEE Transactions on Computers}, volume = {42}, number = {7}, issn = {00189340}, year = {1993}, pages = {769779}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.237718}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for SpecialPurpose Processors IS  7 SN  00189340 SP769 EP779 EPD  769779 A1  K. Kota, A1  J.R. Cavallaro, PY  1993 KW  numerical accuracy; hardware tradeoffs; CORDIC arithmetic; specialpurpose processors; coordinate rotation digital computer; realtime signal processing; Yreduction mode; inverse tangent function; floatingpoint CORDIC; implementation complexity; hybrid architecture; specialpurpose arrays; digital arithmetic; signal processing. VL  42 JA  IEEE Transactions on Computers ER   
The coordinate rotation digital computer (CORDIC) algorithm is used in numerous specialpurpose systems for realtime signal processing applications. An analysis of fixedpoint CORDIC in the Yreduction mode, which allows computation of the inverse tangent function, shows that unnormalized input values can result in large numerical errors. The authors describe two approaches for tackling the numerical accuracy problem. The first approach builds on a fixedpoint CORDIC unit and eliminates the problem by including additional hardware for normalization. A method for integrating the normalization operation with the CORDIC iterations for efficient implementation in O(n/sup 1.5/) hardware is provided. The second solution to the accuracy problem is to use a floatingpoint CORDIC unit but reduce the implementation complexity by using a hybrid architecture. Arguments to support the use of such an architecture in certain specialpurpose arrays are presented.
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