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Designing Optimum One-Level Carry-Skip Adders
June 1993 (vol. 42 no. 6)
pp. 759-764

The author shows how to design one-level carry-skip adders that attain very high speeds. One-level carry-skip adders are very fast adders that are hardly more complex than the much-slower ripple adders. The design procedure allows the use of realistic component delays obtained by simulation and is technology-independent. An example of a 64-b, 1 mu m CMOS adder is given. This adder achieves an add time of 6.23 ns, measured by SPICE simulation with realistic loads. This delay figure excludes sum buffering delays, which depend on the particular application of the adder. The combination of high-speed and simplicity makes one-level carry-skip adders attractive for applications in highly parallel systems.

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Index Terms:
carry-skip adders; one-level; SPICE simulation; 64 bit; 1 micron; 6.23 ns; adders; digital simulation; logic design.
Citation:
V. Kantabutra, "Designing Optimum One-Level Carry-Skip Adders," IEEE Transactions on Computers, vol. 42, no. 6, pp. 759-764, June 1993, doi:10.1109/12.277297
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