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H.W. Alnuweiri, "A New Class of Optimal BoundedDegree VLSI Sorting Networks," IEEE Transactions on Computers, vol. 42, no. 6, pp. 746752, June, 1993.  
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@article{ 10.1109/12.277299, author = {H.W. Alnuweiri}, title = {A New Class of Optimal BoundedDegree VLSI Sorting Networks}, journal ={IEEE Transactions on Computers}, volume = {42}, number = {6}, issn = {00189340}, year = {1993}, pages = {746752}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.277299}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  A New Class of Optimal BoundedDegree VLSI Sorting Networks IS  6 SN  00189340 SP746 EP752 EPD  746752 A1  H.W. Alnuweiri, PY  1993 KW  boundeddegree; VLSI sorting networks; optimal VLSI sorters; rotatesort; enumerationsort; time complexity; reducedarea; Kshuffle layouts; logic design; optimisation; sorting; VLSI. VL  42 JA  IEEE Transactions on Computers ER   
Minimumarea very large scale integration (VLSI) networks have been proposed for sorting N elements in O(log,N) time. However, most of such networks proposed have complex structures, and no explicit network construction is given in others. New designs of optimal VLSI sorters that combine rotatesort with enumerationsort to sort N numbers, each of length w (1+ in )logN bits (for any constant in <0), in time T in ( Omega (logN), Theta square root (NlogN)). The main attributes of the proposed sorters are a significantly smaller number of sorting nodes than in previous designs and smaller constant factors in their time complexity. The proposed sorters use a new class of reducedarea Kshuffle layouts to route data between sorting stages. These layouts can be also used to provide explicit designs for the columnsort technique developed by F.T. Leighton (1985).
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